February 23 , 2004 Washington, D. C. ** PUBLIC VERSION ** TED STATES OF AMRICA FEDERA TRAE COMMSSION OFFICE OF ADMISTRATIVE LAW JUGES Docket No. 9302 In the Matter of RABUS INC. A CORPORATION INITIAL DECISION Before: Stephen 1. McGuire Chief Administrative Law Judge FEDERA TRAE COMMSSION APPEARCES FOR THE PARTIES Counsel Supporting the Complaint: M. Sean Royall Geoffey D. Oliver Patrick 1. Roach Of Counsel: Malcom L. Catt Robert P. Davis Michael A. Franchak Theodore A. Gebhard Andrew Heimert Charlotte Manning Lisa D. Rosenthal Sarah E. Schroeder Jerome A. Swindell John C. Weber Cary E. Zuk BURAU OF COMPETITION FEDERA TRAE COMMSSION Washington, D.C. 20580 Counsel for Respondent: Gregory P. Stone Steven M. Perry Peter A. Detre Sean P. Gates MUGER, TOLLES & OLSON LLP 355 South Grand Avenue, 35th Floor Los Angeles, California 90071- 1560 A. Douglas Melamed Kenneth A. Bamberger WIMER, CUTLER & PICKERIG LLP 2445 M Street, N. Washington, D. C. 20037 Sean C. Cunningham John M. Guaragna GARY, CARY, WAR & FREIDENRCHLLP 401 "B" Street, Suite 2000 San Diego, California 92101 II. TABLE OF CONTENTS PART ONE: INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FEDERA TRAE COMMSSION COMPLAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 II. RESPONDENT' S ANSWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 III. ISSUES PRESENTED . . . . . . . . . . . . . . . . . . . 3 IV. PROCEDUR BACKGROUN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 EVIDENCE. . . . . . . . . . . . . . . . . . . . . . . 5 VI. SUMARY OF THE DECISION . . . . . . . . . 6 PART TWO: FININGS OF FACT . . . . . . . . . 8 DRA AN THE INVENTIONS OF DRS. F AR ALD AN HOROWITZ . . . . . . 8 A. DRA Applications in Computer Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1. DRA Defined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. The Production of DRAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a. The DRA Manufacturing Process. . . . . . . . . . . . . . . . . . . . . . . 8 b. The Various Phases of DRA Development. . . . . . . . . . . . . . . . 9 c. Design Modification During DRA Production . . . . . . . . . . . . 10 The Memory Bottleneck Problem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Farmwald' s and Horowitz s Inventions Solve the Memory Bottleneck Problem by Addressing Numerous Issues . . . . . . . . . . . . . . . . . . . . 1. Electrical Issues . . . . . . . 14 2. Clocking Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. The Memory Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAUS: COMPAN DEVELOP.MENT AN PUBLIC PROMOTION OF TECHNOLOGY . . . . . . . . . . . A. The Founding of Ram bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1. Securing Venture Capital Funding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2. Early Business Plan for the FarmwaldlHorowitz Inventions. . . . . . . . . . 17 The RDRA Technology. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 The 1990 Business Plan . . . . . . . 20 RDRA Promotion and Licensing Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Presentation of the Rambus Inventions to the DRA Industry. . . . . . . . . . . . . 21 1. Rambus Visits to DRA Manufacturers and Systems Companies. . . . . 21 Preparation and Description of the Rambus Inventions Through Various Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 a. The May 1990 Techncal Description. . . . . . . . . . . . . . . . . . . . . 23 b. The November 1990 Technical Description. . . . . . . . . . . . . . . . 23 c. Siemens Responds With a List of Questions About Rambus Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 d. The April 1991 Techncal Description . . . . . . . . . . . . . . . . . . . . 25 The March 1992 Press Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Press Coverage: The March 1992 Microprocessor Report Aricle . . . . . . . . . . 27 Rambus s Disclosure ofInventions Through Public Documents . . . . . . . . . . . . 27 1. The 1992 Marketing Brochure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2. Publications Describing the First Rambus DRA . . . . . . . . . . . . . . . . . 28 Presentations of the Proprietary RDRA Technology and Nondisclosure Agreements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 The June 1992 Business Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Rambus Patent Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1. The ' 898 Patent Application . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . 30 2. The ' 703 Patent . . . . . . . . . . . 32 3. The PCT Application . . . 32 4. The ' 898 and PCT Applications Describe Numerous Inventions . . . . . . 32 a. Description of Access Time Registers . . . . . . . . . . . . . . . . . . . . 34 b. Description of Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 c. Description of Bus Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 d. Description of Variable Delay Circuitry With a Feedback Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Review of the ' 898 or PCT Application Should Have Raised Concerns That Rambus Might Be Able to Obtain Claims Over the Four Technologies at Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 JEDEC IS A COLLABORATIVE STANAR SETTING BODY FOR THE SEMICONDUCTOR INUSTRY ....................................... A. Early History of JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 B. The Purpose and Function ofJEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 C. The Organization ofJEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1. Member Companies . . . . 38 2. The JEDEC Council, Board of Directors and Offcers. . . . . . . . . . . . . . 39 3. The JC 42 Commttee. . . . . . 40 The Standard Development Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Rambus s Involvement in JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1. Rambus s Participation in JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Rambus Representatives Learn About the EINJEDEC Patent Policy . . 42 3. Rambus Continued to Stay Abreast of JEDEC and SyncLink Activities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 III. IV. EARY DEVELOPMENT AN ADOPTION OF JEDEC DRA STANARS. . . 44 A. The Initial SDRA Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1. Demand for a New Generation of Memory . . . . . . . . . . . . . . . . . . . . . . 44 2. Proposal of a Fully Synchronous DRA . . . . . . . . . . . . . . . . . . . . . . . . 45 3. Inclusion of Programmable CAS Latency and Burst Length . . . . . . . . . 47 4. Presentations of Additional Technologies . . . . . . . . . . . . . . . . . . . . . . . 50 a. Low Voltage Swing Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . 50 b. Dual Bank Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 c. Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 d. Source Synchronous Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . 51 e. Externally Supplied Reference Voltage ................... 52 5. Adoption of the SDRA Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6. Subsequent Proposals: Costs, CAS Latency and SDRA Lite. . . . . . . 53 B. . DDR SDRA - The Next Generation SDRA . . . . . . . . . . . . .. . . . . . . . . . . 54 1. Wark Within and Outside of JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2. Future Synchronous SDRA Features. . . . . . . . . . . . . . . . . . . . . . . . . 56 a. Presentation of Programmable CAS Latency and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b. Discussion ofPLL/DLL . . . . . . . . . . . c. Consideration of Dual Edge Clocking . . . . . . . . . . . . . . . . . . . . 59 Subsequent Proposed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 a. Externally Supplied Reference Voltage ................... 61 b. Source Synchronous Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . 61 Adoption of the DDR SDRA Standard . . . . . . . . . . . . . . . . . . . . . . . 61 Features Incorporated into the Standard. . . . . . . . . . . . . . . . . . . . . . . . . 62 a. On-Chip DLL ...................................... 62 b. Dual Edge Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c. Programmable CAS Latency and Burst Length . . . . . . . . . . . . . 62 Interoperability: The Effect of JEDEC' s Specifications versus Manufacturers Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RAIN AN SYNCLIN, THE SYNCLIN CONSORTIU, INTEL DRA MAACTURRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 A. The IEEE RamLink and SyncLink Working Groups. . . . . . . . . . . . . . . . . . . . . 63 1. The IEEE Membership Requirements and Lack of Patent Disclosure Obligations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 RamLink Was Developed to Standardize a New Future Memory Bus . . 63 The IEEE SyncLink Project Emanated From and Modified the Proposed RamLink Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Presentation of the RamLink/Synclink Architecture at JEDEC - Rambus Elects Not to Comment On Its Intellectual Property Position . . . . . . . . 64 Richard Crisp Indicates That the SyncLink Proposal May Infnge VI. Rambus Patents But Declines To Comment Regarding Rambus Intellectual Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Hyundai Negotiates "Other DRA Provision As Part ofIts RDRA License Agreement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 66 The SyncLink Consortium . . . . . . 67 1. Formation and Purpose of the Consortium . . . . . . . . . . . . . . . . . . . . . . 67 2. COJ;cern About Patents of Non-Members ....................... 68 3. SyncLink's Activities With Respect to Rambus Patent Applications and Intel' s Anounced Support ofRDRA ........................ Rambus s Relationships With Intel and DRA Manufacturers . . . . . . . . . . . . . 70 1. Rambus Sought Licenses and Support for RDRA From DRA Manufacturers Afer Intel Endorsed RDRA Technology . . . . . . . . . . 70 Intel and RDRA Royalty Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Design, Manufacture, and Supply of Memory Architectures by Micron and Other DRA Manufacturers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Cost Issues Associated With RDRA ......................... Actions by DRA Manufacturers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 The DRA Industry s Approach to Addressing RDRA Problems . . . 80 By 1998 the Rambus- Intel Relationship Was Deteriorating . . . . . . . . . . 81 Techncal Problems and Product Delays With RDRA . . . . . . . . . . . . . 81 Intel' s Announcement That It Would No Longer Support RDRA ... EINJEDEC PATENT POLICY ... .... ...... ....... . .. . ....... . .... .. . . . 83 A. Good Faith Obligations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 B. Open Standards . . . . . . . . . . . . . . . . . . . 85 C. Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1. JEP 21- ............................................... 86 2. JEP 21- . . . . . . . . . . . . . 86 3. EIA Legal Guides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4. EP- FandEP- A........................................ 91 5. ANSI Patent Policy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Committee Forms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 1. Membership Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' 93 2. Meeting Attendance Roster (Sign-In Sheet) ..................... 94 3. Committee Ballots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4. Members' Manual. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 96 5. Patent Tracking List . . . . . 97 Contemporaneous Correspondence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 1. The McGhee Memorandum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Correspondence Regarding the Dell Consent Agreement. . . . . . . . . . . . 98 3. Correspondence Regarding Micron Disclosure . . . . . . . . . . . . . . . . . . . 99 Conduct of Parties in JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 1. SEEQ Issue . . . . . . . . . . . . . . . 101 2. WANG Litigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3. ffM's Patent Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4. Hewlett Packard' s Patent Position ............................ 103 5. Texas Instruments' QUAD CAS Issue . . . . . . . . . . . . . . . . . . . . . . . . 103 6. Micron s Presentation on Burst EDO ......................... 104 7. Hyundai and Mitsubishi' s Presentation on SLDRA ............. 105 Trial Testimony . . . . . . . . . . . . . . . . . . . 105 1. A Policy in Transition. . . . . . . . . . . . . 105 2. Creation of Ambiguity and Confsion Regarding the Policy. . . . . . . . . 106 3. Unsuccessful Efforts to Expand the Patent Policy . . . . . . . . . .. . . . . . 107 4. Changes in Policy Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 a. EIA Patent Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 b. Changes Found in JEP 21-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Conflicts in the Trial Testimony 111 a. Trial Testimony Conficts Regarding Whether the Patent Policy Applied to Patent Applications and Intentions to File Patent Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Trial Testimony Conflicts Regarding Whether Members Should Disclose Actual Claims or Whether a Patent Number Was Suffcient. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Trial Testimony Conflicts Regarding Whether More Than Essential Patents Were Included in the Policy . . . . . . . . . . . . . 113 d. Trial Testimony Conflicts Regarding the Timing of Disclosure. . . . . . . 114 The Scope of the EINJEDEC Patent Policy. . . . . . . . . . . . . . . . . . . . . . . . . . 114 1. Disclosures Were Encouraged and Voluntary . . . . . . . . . . . . . . . . . . . 114 2. Patent Applications or Intentions To File Patent Applications Were Not Covered by the Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Members Were Encouraged To Disclose Patents That Were Essential To Practice the Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 There Was No Duty To Search for Intellectual Property Issues. . . . . . 116 The Policy was Limited To Participants With Actual Knowledge. . . . . 117 The Patent Policy Did Not Apply Afer a Company Withdrew From JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 If Disclosure Was Made, It Was Encouraged No Later Than the Time of Balloting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 VII. JEDEC 42.3 COMMTTEE MEMBERS WERE NOT MISLED BY RAUS ISSUES RELATING TO RAUS INTELLECTUAL PROPERTY. . . . . . . . . . . . 118 A. JEDEC Commttee Leaders and Members Were Fully Aware ofRambus Patents With Respect To Features Being Considered for Incorporation into JEDEC Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 1. Crisp Did Not Mislead JEDEC At the May 1992 Commttee Meeting VIII. RAUS WAS NOT IN VIOLATION OF ANY JEDEC RULES . . . . . . . . . . . . . . 134 A. Rambus Was Not in Violation of the JEDEC Patent Policy. . . . . . . . . . . . . . . 134 B. There Is No Evidence that Crisp, During the Time Rambus Participated in JEDEC, Had Actual Knowledge that Rambus Had Claims that Could Be Asserted Against JEDEC-Compliant SDRA or DDR SDRA Products . . . 134 Rambus Did Not Misappropriate Information From JEDEC . . . . . . . . . . . . . . 136 There Were No Prohibitions Which Precluded Rambus From Seeking Patent Protection For Inventions that Related to JEDEC Standards. . . . . . . . . . . . . . 136 Rambus Followed the Advice ofIts Legal Counsel in Determining Its Legal Obligations to JEDEC .......................................... 138 During the Time ofIts Participation in JEDEC Rambus Had No Intellectual Property Interests That It Would Have Been Required To Disclose Even If Disclosure Was Mandatory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 1. Rambus Had No Patents That It Was Required To Disclose . . . . . . . . 139 a. The ' 327 Patent Contains Various Limitations. . . . . . . . . . . . . 140 b. Rambus Had No Duty To Disclose the ' 327 Patent Based On the Hardell Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Rambus Had No Duty To Disclose the ' 327 Patent Based On the Survey Ballot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Rambus Had No Duty To Disclose the ' 327 Patent Based On the Samsung Presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Complaint Counsel Did Not Provide Suffcient Evidence Determne Whether the Presentations Would Trigger the Patent Policy. . . . . . . . . . . . . 141 Rambus Had No Undisclosed Patent Applications That It Was Required to Disclose, Even if the Policy Required Disclosure . . . . . . . 141 Regarding Rambus s Intent To Seek Patent Rights Over Certain SDRA Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 a. ffM and Siemens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 b. The May 1992 JC 42. 3 Meeting. . . . . . . . . . . . . . . . . . . . . . . . 120 c. PCT Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 d. Afer the May 1992 JC-42. 3 Meeting ................... 123 pcr Application Discussed At the September 1993 Meeting. . . . . . . . 124 The May 1995 JC 42. 3 Meeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 The September 1995 JC 42. 3 Meeting. . . . . . . . . . . . . . . . . . . . . . . . . 127 Rambus Met With Manufacturers and Suppliers . . . . . . . . . . . . . . . . . 128 JEDEC Members Viewed Rambus s Patents As a Collection of Prior Ar ................................................... 129 The Dell Consent Order and Rambus s Last JEDEC Meeting- December 1995 To January 1996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Ongoing Discussions of Rambus Patents by JEDEC Members Afer June 1996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1 THE EVIENCE DOES NOT SUPPORT COMPLAIT COUNSEL' ARGUMNT THAT THERE WERE VIABLE ALTERNATIVES TO RAUS' TECHNOLOGIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 A. The Testimony of Professor Jacob Regarding Allegedly Viable Alternatives Is Not Persuasive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Complaint Counsel Did Not Prove That There Were Viable Alternatives to the Rambus Technologies Adopted in the SDRA ....................... 167 1. Programmable CAS Latency. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 167 a. Complaint Counsel Did Not Prove That the Use of Fixed CAS Latency Parts Was a Viable Alternative. . . . . . . . . . . . . . . . . . 167 Complaint Counsel Did Not Prove That Programming CAS IX. XI. Rambus Withdrew From JEDEC Before Formal Work On the Standardization of the DDR SDRA Began. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Document Destruction by Rambus .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 RAUS HAS MONOPOLY POWER IN THE RELEVANT MARTS . . . : . . . 149 A. Relevant Markets. . . . . . . . . . . . . . . . . . . 149 1. Product Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2. Geographic Market. . . . 149 Monopoly Power . . . . . . . . . . . . . 150 1. Market Share . . . . . . . . 150 2. Assertion of Patents ...................................... 150 3. JEDEC Standardization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 a. Rambus s Market Power Is Not Attributable to the Inclusion of Its Technology In JEDEC Standards. . . . . . . . . . . . . . . . . . 152 Rational Manufacturers and a Rational Standard Setting Organization Would Have Stil Adopted the Rambus Technologies Had Disclosure Occurred. . . . . . . . . . . . . . . . . . 155 Intel' s Choice ofRDRA Conferred Market Power, Not JEDEC Standardization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 THE CHALENGED CONDUCT WAS NOT EXCLUSIONARY. . . . . . . . . . . . . . 157 A. Rambus Had a Legitimate Business Justification For Not Disclosing its Proprietary Patent Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Rambus s Conduct Did Not Impact Equal or Superior Alternatives . . . . . . . . 161 The "Commercial Viability" Analysis of Complaint Counsel' s Economic Expert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 The Assumption by Complaint Counsel' s Economic Expert that Rambus Knowingly Assumed the Risk Of Losing Its Ability To Enforce Its Patents. . . 163 The Assumption by Complaint Counsel' s Economic Expert That Rambus Violated a JEDEC Rule or Made Misrepresentations to JEDEC . . . . . . . . . . . 164 The Economic Evidence Regarding "Hold Up" and Disclosure Costs . . . . . . . 165 Vll Latency with Fuses Was a Viable Alternative. . . 171 Complaint Counsel Did Not Prove That Scaling CAS Latency With Clock Frequency Was a Viable Alternative . . . . . . . . . . . 173 Complaint Counsel Did Not Prove That Using Dedicated Pins to Identify the Latency Was a Viable Alternative. . . . . . . . . . . 174 Complaint Counsel Did Not Prove That Identifying CAS Latency in the Read Command Was a Viable Alternative. . . . . 176 Complaint Counsel Did Not Prove That Staying with Asynchronous Technology Was a Viable Alternative. . . . . . . . 177 Programmable Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 a. Complaint Counsel Did Not Prove That the Use of Pi xed Burst Length Parts Was a Viable Alternative . . . . . . . . . . . . . . . . . . 179 Complaint Counsel Did Not Prove That Programming Burst Length With Fuses Was a Viable Alternative. . . . . . . . . . . . . . 181 Complaint Counsel Did Not Prove That Using Dedicated Pins To Identify Burst Length Was a Viable Alternative . . . . . . . . . 182 Complaint Counsel Did Not Prove That Explicitly Identifying Burst Length in the Read Command Was a Viable Alternative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Complaint Counsel Did Not Prove That Using a Burst Terminate Command Was a Viable Alternative . . . . . . . . . . . . 183 Complaint Counsel Did Not Prove That Using CAS Pulse To Control Data Output Was a Viable Alternative 185 Given the Cost-Performance Differences, an Eco omically Rational DRA Manufacturer Would Have Adopted and Licensed the Rambus Technologies Incorporated In SDRA IfIt Had Known Of Ram bus Royalty Rates In Advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Complaint Counsel Did Not Prove That There Were Viable Alternatives To the Specified Rambus Technologies Adopted In DDR SDRA ........... 188 1. Dual-Edge Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 a. Complaint Counsel Did Not Prove That Interleaving On-Chip Banks Was a Viable Alternative. . . . . . . . . . . . . . . . . . . . . . . . 189 Complaint Counsel Did Not Prove That Interleaving On-Module Ranks Was a Viable Alternative. . . . . . . . . . . . . . . . . . . . . . . . 190 Complaint Counsel Did Not Prove That Increasing the Number of Pins on the DRA Was a Viable Alternative. . . . . . . . . . . . 192 Complaint Counsel Did Not Prove That Increasing the Number of Pins on the Module Was a Viable Alternative . . . . . . . . . . . 194 Complaint Counsel Did Not Prove That Doubling the Clock Frequency Was a Viable Alternative . . . . . . . . . . . . . . . . . . . . 194 Complaint Counsel Did Not Prove That Using Simultaneous Bi-directional I/O Drivers Was a Viable Alternative. . . . . . . . . 196 Complaint Counsel Did Not Prove That Using Toggle Mode Vll Was a Viable Alternative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 On-Chip DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 a. Complaint Counsel Did Not Prove That Putting a DLL On the Memory Controller Was a Viable Alternative. . . . . . . . . . . . . . 199 Complaint Counsel Did Not Prove That Putting a DLL On the Module Was a Viable Alternative . . . . . . . . . . . . . . . . . . . . . . 199 Complaint Counsel Did Not Prove That Using a Verner Method To Account For Skew Was a Viable Alternative. . . . . 201 Complaint Counsel Did Not Prove That Increasing the Number of Pins on the DRA Was a Viable Alternative. . . . . 202 Complaint Counsel Did Not Prove That Relying on the DQS Data Strobe Was a Viable Alternative . . . . . . . . . . . . . . . . . . . 202 Complaint Counsel Did Not Prove That Read Clocks Were a Viable Alternative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Given the Cost-Performance Differences, Economically Rational DRA Manufacturers Would Have Adopted and Licensed the Rambus Technologies Incorporated in DDR and SDRA ................ 203 EVEN ASSUMG THAT ALTERNATIVES DID EXIST, JEDEC WOULD NOT HAVE REJECTED THERAUS TECHNOLOGIES .... ........ . ......... 205 A. Whether JEDEC Would Have Adopted Alternatives To Rambus s SDRA and DDR Technologies Had Rambus Made Additional Disclosures. . . . . . . . . 205 JEDEC Might Not Have Sought a RA Assurance From Rambus Even if Rambus Had Made Disclosures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 If JEDEC Had Sought a RA Assurance, It Would Stil Have Adopted Rambus s Technologies . . . . . . . . . . . . 210 1. Rambus Would Have Given a RA Assurance. . . . . . . . . . . . . . . . . 210 2. It is Unlikely There Would Have Been Any Ex Ante Negotiations. . . . 213 3. JEDEC Would Have Adopted Rambus s Technologies with Rambus RA Assurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 XII. XIII. ANALYSIS OF THE BUT/FOR WORLD HYOTHESIS . . . . . . . . . . . . . . . . . . . . 218 A. The Revealed Preference Theory - JEDEC Continued To Select Rambus Technologies Even While Rambus Was Asserting Its Patent Rights . . . . . . . . 218 1. Proposed Alternatives Not Adopted By JEDEC ................. 219 a. Alternative To On-Chip PLL in DDR2 .................. 220 b. JEDEC Selection of Programmable CAS Latency . . . . . . . . . . 220 c. JEDEC Selection of Programmable Burst Length . . . . . . . . . . 221 d. JEDEC Selection of Dual-Edge Clocking . . . . . . . . . . . . . . . . 221 JEDEC Continued to View Rambus Patents As A Collection Of Prior ...................................................... 222 XIV. RAUS' S ROYALTY RATES AR IN FACT REASONABLE xv. NONDISCRIATORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 A. Rambus s Royalty Rates Are Reasonable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 1. The JEDEC Rules Defined "Reasonable" as the Rate Determned By the Market . . . . . . . . . . . 225 Rambus s Royalties Are Comparable To Other Licensing Rates in the Industry and Are "Reasonable" Under the JEDEC Rules. . . . . . . . . . . 226 Rambus s Royalty Rates Are Nondiscriminatory. . . . . . . . . . . . . . . . . . . . . . . 229 1. JEDEC Has Left the Definition of "Nondiscriminatory" to the Market and the Courts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 The Economic Evidence That Rambus s Royalty Rates Are Nondiscriminatory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 THE EVIENCE DOES NOT ESTABLISH THAT THE DRA INUSTRY IS LOCKED IN TO USING THE RAUS TECHNOLOGIES. . . . . . . . . . . . . . . . . . 231 A. An Historical Look at How the DRA Industry Transitions To New Technologies . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 1. Statistical Evidence of Co-Existing DRA Standards. . . . . . . . . . . . . 231 2. Industry Redesign of DRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 3. The Manufacture of Multiple DRAs to Accommodate New Technology. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 4. Coordination of New Industry Standards. . . . . . . .. . . . .. . . . . . . . . . 236 Switching Costs Do Not Support Theory ofIndustry Lock In. . . . . . . . . . . . . 238 1. Such Costs Are Not Prohibitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 2. Coordination Issues Would Not Preclude Switching to New Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 PART THRE: ANALYSIS AN CONCLUSIONS OF LAW . . . . . . . . . . . . . . . . . . . . . . 241 II. III. PROCEDUR ISSUES. . . . . . . . . . . . . . . . . . . 241 A. Standard of Proof. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 B. The Adverse Presumptions Are Not Material to the Disposition of the Case. . 243 1. The First and Second Adverse Presumptions Are Moot. . . . . . . . . . . . 244 2. The Five Remaining Adverse Presumptions Are Not Relevantto Any Material Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 3. A "Missing Witness" Inference Is Not Appropriate. . . . . . . . . . . . . . . 245 The Infineon Litigation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Jurisdiction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 OVERVIW OF VIOLATIONS ALLEGED ............................... 248 ELEMENTS OF LIABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 A. Possession of Monopoly Power in the Relevant Markets. . . . . . . . . . . . . . . . . 250 1. Relevant Markets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 a. Geographic Market. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 b. Product Markets . . . . . 251 2. Monopoly Power . . . . . 251 No Pattern of Anticompetitive Acts and Practices. . . . . . . . . . . . . . . . . . . . . . 253 1. The Legal Theory Upon Which Complaint Counsel Challenge Respondent's Conduct Lacks a Reasonable Basis in Law . . . . . . . . . . 254 Duties Upon Whch Complaint Counsel Base Their Challenge Must Be Clear. ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 The Evidence Presented at Trial Does Not Provide a Factual Basis for Finding a Pattern of Anticompetitive Acts and Practices . . . . . . . . . . . 260 a. No Duty to Disclose Intellectual Property Based on Good Faith . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 No Duty to Disclose Intellectual Property Based on Open Standards . . . . . . . . . 261 No Duty to Disclose Intellectual Property Based on the EINJEDEC Patent Policy. . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 i. Disclosure of Intellectual Property Under the EINJEDEC Patent Policy Was Voluntary . . . . . . . . . . 265 The EINJEDEC Patent Policy Was Limited to Issued Patents, Not to Patent Applications or Intentions to File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 The EINJEDEC Patent Policy Applied to Essential Patents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 The EINJEDEC Patent Policy Was Triggered At the Time of Submitting Committee Ballots. . . . . . . . . . . . . 271 The Unsuccessful Attempt to Expand the EINJEDEC Patent Policy Created Ambiguity and Confsion. . . . . . . . . . . . . . . . . 272 Rambus Had No Patents or Pending Patents That Would Have Been Required to be Disclosed by the EINJEDEC Patent Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 i. SDRA . . . . 274 ii. DDR-SDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 The Evidence Presented at Trial Does Not Provide a Factual Basis for Finding That Rambus Made Afrmative, Misleading Statements to JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Amendments to Claims to Broaden Patent Applications Were Not Improper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 No Exclusionary Conduct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 1. Exclusionary Conduct Defined . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 286 2. Legitimate Business Justifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 3. Conduct Before Standard Setting Organizations . . . . . . . . . . . . . . . . . 289 4. Violations of Extrinsic Duties or Deception Afecting Consumers Not Exclusionary Conduct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 11. 111. IV. No Intent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 1. Intent Defined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 2. Complaint Counsel Have Not Demonstrated That Respondent Intended to Mislead or Deceive JEDEC ....................... 297 3. No Inference ofIntent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 4. Other Factors Demonstrating That The Intent Element Is Not Met . . . 299 No Causation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 1. Causation Defined. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 300 2. No Causal Link Between JEDEC Standardization and Respondent's Acquisition of Monopoly Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 a. Rambus Did Not Acquire Monopoly Power by Virtue of JEDEC's Standard Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Rambus Acquired Monopoly Power as a Result of its Superior Technology and Intel's Choice of its Technology. . . . . . . . . . . 303 3. No Reasonable Reliance by JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 4. No Inference of Causation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 No Anticompetitive Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 1. Anticompetitive Effects Defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 2. Complaint Counsel Have Not Demonstrated That There Were Viable Alternatives to Rambus Technologies . . . . . . . . . . . . . . . . . . . . . . . . . 312 a. Programmable CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . 313 b. Programmable Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . 314 c. Dual-edge Clocking. . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 d. On-Chip DLL ..................................... 315 Analysis of the Economic Evidence. . . . . . . . . . . . . . . . . . . . . . . . . . . 316 a. The Methodology Used by Complaint Counsel' s Economic Expert Is Flawed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 In the "But/For" World, JEDEC Would Not Have Rejected the Rambus Technologies Even if Alternatives Did Exist and Rambus Had Made the Additional Disclosures. . . . . . . . . . . . . 319 JEDEC's " Revealed Preference" For Rambus s Technologfes .. ...... ... ............... .... . . .......... . .. ... 322 Complaint Counsel Have Not Demonstrated That Rambus s Conduct Resulted in Higher Prices to Consumers . . . . . . . . . . . . . . . . . . . . . . . 323 a. Rambus s Royalty Rates Are Reasonable. . . . . . . . . . . . . . . . . 324 b. Rambus s Royalty RateS Are Nondiscriminatory . . . . . . . . . . . 325 JEDEC Is Not Locked In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 IV. SUMY OF LIABILITY ........................................... 329 PART FOUR: SUMY OF CONCLUSIONS OF LAW ......................... 329 ORDER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 XlI PART ONE: INTRODUCTION This Initial Decision is divided into four parts. Part One is the introduction, which includes a summary of the allegations contained in the Complaint; the defenses asserted in Respondent' s Answer; the issues presented; the procedural background; a comment on the evidence; and a summary of the decision. Part Two contains the separately numbered findings of fact. Part Three contains the analysis and conclusions oflaw, which provides an overview ofthe legal theories asserted by Complaint Counsel; sets forth the applicable law on each of the elements necessary to find a violation; and then applies the law to the facts established at trial. Part Four contains the summary of the conclusions oflaw and the Order of the Court. FEDERAL TRADE COMMISSION COMPLAINT The Federal Trade Commssion ("FTC") issued its Complaint in this matter on June 18 2002. The Complaint charges that Respondent, Rambus Inc. , a corporation, violated Section 5 of the Federal Trade Commssion Act ("FTC Act"), as amended. 15 U.S. c. 45. The Complaint charges Respondent with three violations. The first violation charges that Respondent engaged in a pattern of anti competitive and exclusionary acts and practices, whereby it obtained monopoly power in the synchronous DRA technology market and narrower markets encompassed therein, in violation of Section 5 of the FTC Act. (Complaint,- 122). The second violation charges that Respondent engaged in a pattern of anticompetitive and exclusionary acts and practices with a specific intent to monopolize the synchronous DRA technology market and narrower markets encompassed therein, resulting, at a minimum, in a dangerous probability of monopolization in each ofthe markets, in violation of Section 5 of the FTC Act. (Complaint ,- 123). The third violation charges that Respondent engaged in a pattern of anti competitive and exclusionary acts and practices, whereby it unreasonably restrained trade in the synchronous DRA technology market and narrower markets encompassed therein, which acts and practices constitute unfair methods of competition in violation of Section 5 of the FTC Act. (Complaint ,- 124). The Complaint alleges that Respondent participated in the work of the JEDEC Solid State Technology Association ("JEDEC"), an industry standard setting organization in which Respondent was a regular participant, without making it known to JEDEC or to its members that Respondent sought to obtain patents on technologies adopted in the relevant JEDEC standards. (Complaint,-,- 2 , 44, 45 , 46). Respondent's alleged scheme further entailed perfecting its patent rights over these same technologies and then, once the standards had become widely adopted within the DRA industry, enforcing such patents worldwide against companies manufacturing memory products in compliance with the JEDEC standards. (Complaint,-,- 2 , 45 , 46). Respondent is alleged to have concealed information in violation ofJEDEC' s operating rules and procedures which Complaint Counsel argue imposed upon JEDEC members an obligation to "disclose any patents, or pending patent applications, involving the standard-setting work." (Complaint,-,- 20, 21 , 24, 79). In addition, the Complaint alleges a "basic rule" of JEDEC to avoid a,nticompetitive activity and a commtment to avoid, where possible incorporation of patented technologies. (Complaint,-,- 17 22). The Complaint alleges that Respondent violated these duties by conveying to JEDEC the materially false and misleading impression that it possessed no relevant intellectual property rights. (Complaint,-,- 2 , . 80). The Complaint further alleges that Respondent s conduct caused anticompetitive effects including increased royalties, increase in the price of synchronous DRA and products incorporating synchronous DRA, decreased incentives to produce memory using synchronous DRA technology, and harms to standard setting organizations and activities. (Complaint ,-,- 119, 120). ll. RESPONDENT' S ANSWER In its Answer filed on July 29, 2002, Respondent alleged as an affrmative defense that the Complaint failed to state a claim under Section 5 of the FTC Act. The Answer denied the material allegations of the Complaint and asserted that the evidence would show that JEDEC' rules and policies did not impose, and were not commonly understood to impose, the disclosure obligations set out in the Complaint. (Answer, pp. 1-2). Respondent asserted in its Answer that the evidence would show that it did not have, until after it left JEDEC, any undisclosed patents or patent applications that contained claims reading on devices manufactured in accordance with any JEDEC standard. (Answer, p. 2). Respondent also asserted in its Answer that the evidence would show that JEDEC did not rely on any purported silence on Respondent's part at JEDEC meetings and instead chose to adopt certain technologies because ofthe cost/performance advantages of those technologies and the absence of reasonable alternatives. (Answer, p. 2). Respondent's Answer asserted that in light of the absence of a duty to disclose , in light of the absence of pending claims reading on JEDEC standards, and in light of the other evidence to be considered at trial, it would be clear that Respondent' s alleged failure to disclose its potential intellectual property claims had no anticompetitive effect in any market and that Respondent had not violated Section 5. (Answer, pp. 1-3). il. ISSUES PRESENTED The issues presented in this case are: (1) whether Respondent engaged in a pattern of deceptive, exclusionary conduct by subverting an open standards process; (2) whether Respondent utilized such conduct to capture a monopoly in technology-related markets; (3) whether Respondent' s challenged conduct violated principles of antitrust law; and (4) whether Respondent' s conduct resulted in anti competitive injury. IV. PROCEDURAL BACKGROUND On June 18, 2002, the Commssion issued its Complaint. This case was initially assigned to Administrative Law Judge ("ALr') James P. Timony. Rambus filed a motion to stay the proceeding until the Federal Circuit issued its decision in Rambus Inc. v. Infineon Technologies an appeal of a jury verdict against Rambus. The Federal Circuit reversed the jury verdict of fraud and remanded the case, as discussed more fully in Part III, Section I. C. An Order Denying Motion for Stay was issued in this case on July 18 2002. On July 29 2002, Rambus filed its Answer in this matter. On February 26 2003 , ALJ Timony issued an Order On Complaint Counsel' s Motions For Default Judgment and For Oral Argument which imposed seven rebuttable presumptions against Rambus based on a finding of intentional destruction of evidence. This Order is discussed in Part III, Section I.B. On February 28 2003 , ALJ Timony retired from federal service. Stephen 1. McGuire was subsequently appointed FTC Chief Administrative Law Judge and assigned the Rambus matter. Trial in this proceeding commenced on April 30, 2003. The 54 day administrative hearing produced a voluminous evidentiary record including 44 live witnesses, 1 770 admitted exhbits nearly 12 000 pages of trial transcript, and hundreds of pages of deposition transcripts. The last day on which testimony was received was August 1 , 2003. The paries then filed Post-Trial Briefs, Proposed Findings of Fact, and Conclusions of Law, and replies thereto. Closing arguments and oral examination by the Court was conducted on October 8 2003. Following the closing arguments, the hearing record was closed pursuant to Commssion Rule 3.44(c), by Order dated October 9, 2003. Due to the exceptional circumstances of the complexity of the issues presented, the volumes of evidence introduced at trial, and review of the comprehensive proposed findings offact and post-hearing briefs, it was necessary to extend the deadline for filing the Initial Decision within one year of the issuance of the Complaint. By Order dated December 23 , 2003 the Commssion also extended the time for filing the Initial Decision within 90 days of the close of the hearing record until February 17, 2004. EVIENCE The Initial Decision is based on the transcript of the testimony, the exhbits properly admitted in evidence, and the proposed findings of fact, briefs, conclusions of law, and replies thereto filed by the parties. Once a finding of fact is established, it is cited to in subsequent sections or in the analysis by the designation " The parties submitted extensive post-trial briefs and reply briefs. The Initial Decision addresses only material issues of fact and law. Proposed findings offact not included in the This opinion uses the following abbreviations for citations: Compo - Complaint F. - Finding of fact CX - Complaint Counsel Exhbit RX - Respondent Exhbit JX - Joint Exhbit Tr. - Transcript of Testimony before the Administrative Law Judge Dep. - Transcript of Deposition Stip. - Stipulation CCPFF - Complaint Counsel' s Proposed Findings of Fact CCPHB - Complaint Counsel' s Post-Hearing Brief CCPHR - Complaint Counsel' s Post-Hearing Reply Brief RPHB - Respondent's Post- Hearing Brief RPHR - Respondent's Post-Hearing Reply Brief Initial Decision were rejected, either because they were not supported by the evidence or because they were not dispositive to the determination of the allegations contained in the Complaint. The Commssion has held that Administrative Law Judges are not required to discuss the testimony of each witness or all exhbits that are presented during the administrative adjudication. In re Amrep Corp. 102 F.T.c. 1362, 1670 (1983). Further, administrative adjudicators are "not required to make subordinate findings on every collateral contention advanced, but only upon those issues of fact, law, or discretion which are ' material.'" Minneapolis St. Louis Ry. Co. v. United States 361 U.S. 173 , 193-94 (1959). Many of the documents and parts of the oral testimony were received into the record camera. Where an entire document or where certain trial testimony was given in camera treatment for trial, but the portion of the document or the trial testimony utilized in this Initial Decision does not rise to the level necessary for in camera treatment, such information is disclosed in the public version of this Initial Decision, pursuant to Commssion Rule 3.45(a) (the ALJ "may disclose such in camera material to the extent necessary for the proper disposition of the proceeding ). In accordance with 16 c.F.R. ~ 3.45(f), material that has been given in camera treatment is indicated in bold font and braces in the in camera version. Where in camera material had been redacted from the public version of the Initial Decision, braces precede the redacted material. VI. SUMMARY OF THE DECISION Complaint Counsel have failed to sustain their burden of proof with respect all three of the violations alleged in the Complaint. First, the evidence at trial establishes that Complaint Counsel failed to prove the facts they alleged in the Complaint. Second, an analysis of the legal theories advanced by Complaint Counsel demonstrates that there is no legal basis for finding a violation of Section 5 of the Federal Trade Commssion Act, either as based on other antitrust laws or solely as an unfair method of competition. Third, an application of the facts established at trial to the legal theories asserted leads to the conclusion that Complaint Counsel have failed to prove their case. The evidentiary record demonstrates that: (1) the EINJEDEC patent policy encouraged the early, voluntary disclosure of essential patents and Respondent did not violate this policy; (2) the case law upon which Complaint Counsel rely to impose antitrust liability is clearly distinguishable on the facts of this case; (3) Respondent s conduct did not amount to deception and did not violate any "extrinsic duties " such as a duty of good faith to disclose relevant patent information; (4) Respondent did not have any undisclosed patents or patent applications during the time that it was a JEDEC member that it was obligated to disclose; (5) amendments to broaden Respondent's patent applications while a member of JEDEC were not improper , either as a matter of law or fact; (6) by having a legitimate business justification for its actions, Respondent did not engage in exclusionary conduct; (7) Respondent did not intentionally mislead JEDEC by knowingly violating a JEDEC disclosure rule; (8) there is no causal link between JEDEC standardization and Respondent's acquisition of monopoly power; (9) members of JEDEC did not rely on any alleged omission or misrepresentation by Respondent and, if they had, such reliance would not have been reasonable; (10) the challenged conduct did not result in anticompetitive effects, as Complaint Counsel did not demonstrate that there were viable alternatives to Respondent's superior technologies; (11) the challenged conduct did not result in anti competitive effects as the challenged conduct did not result in higher prices to consumers; and (12) JEDEC is not locked in to using Respondent's technologies in its current standardization efforts. For these reasons, Complaint Counsel have failed to sustain their burden to establish liability for the violations alleged. Accordingly, the Complaint is DISMISSED. PART TWO: FINDINGS OF FACT DRAM AND THE INVENTIONS OF DRS. FARMALD AND HOROWITZ DRAM Applications in Computer Systems DRAM Defined 1. DRA stands for "dynamic random access memory." (Rhoden, Tr. 266). DRA is a type of electronic memory. (Roden, Tr. 266). DRA is "dynamic" because it needs to be refreshed every fraction of a second. (Rhoden, Tr. 266-67). 2. The primary use for DRA is in computer systems. (Roden, Tr. 267-68; Gross, Tr. 2272-73). 3. DRAs are also used in a wide range of other products involving computer systems. (Sussman, Tr. 1362). These products include printers, PDAs (personal digital assistants), and cameras. (Kellogg, Tr. 4986-87; Tabrizi, Tr. 9126-27; Krashinsky, Tr. 2770-71; Farmwald, Tr. 8206-07; Gross, Tr. 2272-73). 4. Typically, multiple DRA chips are placed on a memory module, which is a small printed circuit board. (Roden, Tr. 272-73). The module containing the DRA chips connects to a motherboard. (Rhoden, Tr. 270 273). In some applications, such as graphics cards, the DRA chips are not put in memory modules. (Wagner, Tr. 3871-72). 5. A DRA is made up of a number of cells. (Rhoden, Tr. 359). Information is stored in the cell capacitor as either a high or low voltage. (Roden, Tr. 359). The cells of the DRA are divided into an array via a series of rows and columns with the cells located at the intersections of those rows and columns. (Roden, Tr. 359-60). Access to the cell capacitor is made by activating a transistor, which transfers the voltage in the capacitor to a column, also known as a bit line. (Roden, Tr. 359-60). 6. In order for a DRA to have any value, it must be compatible and interoperable with the other components in the same specific system that include the DRA. (Peisl, Tr. 4410; CX 1075 at 1; Heye, Tr. 3655-65; Jacob, Tr. 5562-66). The Production of DRAMs The DRAM Manufacturing Process 7. The starting point in the manufacturing process is a bare silicon wafer. (Becker, Tr. 1116- 17). 8. During the course of the manufacturing process, successive layers are built up on the silicon wafer. (See generally Becker, Tr. 1116-32). DRAs require as many as twenty-two . distinct layers. (Becker, Tr. 1131). Each layer requires a series of manufacturing steps. (Becker Tr. 1131-32). Processing the wafer takes about four hundred manufacturing steps. (Becker, Tr. 1118, 1131). 9. The manufacturing process is nonlinear, meaning that a wafer wil reenter different processing areas of the fab a number oftimes. (Becker, Tr. 1118). A processed wafer contains hundreds of individual DRA chips. (Becker, Tr. 1117). 10. The processed wafer is electrically tested in order to find the good chips. (Becker Tr. 1132-34). Such testing, however, does not identify all of the die with disqualifying defects. More stringent testing is only possible after the die have been packaged. (Geilhufe, Tr. 9570). 11. Afer testing, the wafer is cut into individual DRAs. (Becker, Tr. 1132-34). The individual chips are then bonded to a metal lattice like structure called a lead frame and are covered with a black hard plastic mold compound. (Becker, Tr. 1132-34). 12. Afer packaging, the good chips are built into components and tested again. (Becker Tr. 1135-36). 13. The tested components may also be assembled onto circuit boards to create modules and are further tested. (Becker, Tr. 1135; see generally Becker, Tr. 1132-36 (describing the process of how the chips are built into components and connected to modules)). 14. The largest part of a DRA, approximately ninety percent of the active area, consists of the memory array, that is the memory cells and related circuitry. (Geilhufe, Tr. 9560). The remaining ten percent consists of peripheral circuitry. (Geilhufe, Tr. 9560). Circuitry for implementing the four features at issue here - programmable column address strobe ("CAS" latency, programmable burst length, dual edge clocking, and on-chip delay lock loop ("DLL" ) - are found in the peripheral circuitry. (Geilhufe, Tr. 9559). 15. The vast majority of DRA development costs is spent on the memory arrayportion of the DRA, including the manufacturing process and equipment development. (Geilhufe, Tr. 9560-61). Development costs for the peripheral circuitry are much lower. (Geilhufe, Tr. 9560- 61). The Various Phases of DRAM Development 16. The development ofthe DRA proceeds along a number of "phases" and milestones. Those are the design phase, the layout phase, the simulation phase, the verification phase, tape out, initial silicon, the validation phase, internal qualification phase, and the production phase. (Shirley, Tr. 4141-42; Reczek, Tr. 4306-41). 17. In the design phase, the DRA designers implement the DRA specification as a set of circuit designs or schematics. (Shirley, Tr. 4142-43). 18. In the layout phase, the layout designers take the circuit designs created in the first step and create a representation of the circuit designs. (Shirley, Tr. 4143). 19. In the simulation phase, the design engineers simulate the designs in order to verify that the chips wil perform as intended before they are first manufactured. (Shirley, Tr. 4144). 20. The verification phase involves ensuring that the schematics created in the design phase are in fact represented by the work done in the layout phase. (Shirley, Tr. 4144-45; Reczek, Tr. 4309). 21. Tape out involves the process of transferring the DRA layout onto masks that wil be used in the fabrication ofthe DRA. (Shirley, Tr. 4145). The collection of individual masks necessary to fabricate a DRA design comprises a mask set. (Shirley, Tr. 4147). 22. A mask contains an image that is transferred to the wafer through a process of using light to expose the wafer to the image pattern in the mask and using gasses to etch the resulting pattern into the wafer. (Becker, Tr. 1122-24). 23. At some DRA manufacturers, including Micron Technologies, Inc. ("Micron ), the physical creation of masks is done by specialized firms that provide the service to the DRA manufacturers. (Shirley, Tr. 4145-46). Other DRA manufacturers, including Infneon Technologies ("Infneon ), produce their own masks. (Reczek, Tr. 4312). 24. The mask set, once it is received, is used to create the first physical manfestation the DRA chips on wafers. Those wafers represent a milestone and are referred to as "initial silicon. " (Shirley, Tr. 4147). 25. Initial silicon is then tested in the validation and internal qualification phases to ensure that the DRA on the wafers operate the way they were intended (the validation phase) and that the DRA on the wafers operate appropriately in the expected environments (the qualification phase). (Shirley, Tr. 4148-49). Design Modifcation During DRAM Production 26. The DRA industry transitions between different versions of DRA quite frequently. As a witness from Micron explained: Switching from one product to another, while stil using the same core technology, involves only changing priorities in design and product engineering and may mean some differences in our assembly and test equipment purchases. SDRA, SLDRA, nDRA all use the same fab equipment and core DRA technology. In short, while the flavors might change, it' s stil a DRA. (R 836 at 3) (emphasis added). The Memory Botteneck Problem 27. Dr. Michael Farmwald, one of the two founders of Ram bus, received his bachelor degree in mathematics from Purdue University in 1974. (Farmwald, Tr. 8058). He then earned a Ph.D. in computer science from Stanford University in 1981. (Farmwald, Tr. 8059). Whle a graduate student at Stanford, Dr. Farmwald was in charge of a supercomputer project at Lawrence Livermore National Labs. (Farmwald, Tr. 8059). Afer obtaining his Ph. , he continued to work at Livermore for four years and then founded a company called FTL (which stood for "Faster Than Light"), whose goal was to build very fast computers. (Farmwald Tr. 8060-61). In 1988, Dr. Farmwald went to the University ofIllnois to teach in the computer science department. (Farwald, Tr. 8063-64). 28. While working as a professor at the University of Ilinois, Dr. Farmwald realized, and it was a general perception in the DRA industry, that developments in microprocessor technology would lead to significant speed increases in microprocessors while memory chip performance would not keep up. (Farmwald, Tr. 8063 , 8067). He recognized that the result of these trends would be a "bottleneck" - memory technology would limit computer system performance. (Farmwald, Tr. 8068-69). 29. Moore s law, named after Gordon Moore, founder ofIntel Corp. ("Intel"), predicts that processor speeds wil increase by a factor offour every three years. (Farmwald, Tr. 8068). This "law" has held true for over the last two decades. (Farmwald, Tr. 8068). The performance of DRAs, however, was increasing at a lesser rate; while DRAs were fast in comparison to microprocessors in the early 1980s, as an historical matter, DRA performance had increased very slowly over time. (Farmwald, Tr. 8072). 30. Graphing predicted microprocessor speeds against memory performance Dr. Farmwald predicted an ever increasing gap between microprocessor performance and DRA performance. (Farmwald, Tr. 8071-73). 31. Assuming that the predicted DRA speeds were not improved, Dr. Farmwald projected that the number of DRAs needed to support future microprocessors would become extremely large over time. (Farmwald, Tr. 8073). 32. The increasing number of DRAs needed to support faster computers was also consistent with Dr. Farmwald' s experience that microprocessors were demanding higher and higher bandwidth memory systems ("bandwidth" being the amount of information that can be transferred over a specific period oftime). (Farmwald, Tr. 8076-79). 33. Dr. Farmwald also plotted the projected price for computers, which showed that the cost for computer systems was dropping over time. (Farmwald, Tr. 8074-75). Comparing these projected costs with the number of DRAs that would be required to support the bandwidth needs offaster microprocessors, Dr. Farmwald knew that "there was something broken" - the costs of the thousands of DRAs needed at higher microprocessor speeds would prevent the decline of computer system prices. (Farmwald, Tr. 8075-76). 34. Later, a 1992 Rambus "Corporate Backgrounder" described the issue: " (o)ne of the most serious problems is the chronic speed mismatch between processors and main memory. Designers refer to this as the memory bottleneck. The data transfer rates of memory ICs (integrated circuits) lag far behind a processor s ability to handle the data." (R 81 at 4). 35. To meet the higher bandwidth needs of microprocessors without the overwhelming cost of thousands of DRAs, DRA performance had to increase at a higher rate. (Farmwald Tr. 8076). 36. Years later, Dr. Farmwald' s 1988 observations were recognized by others in the industry. For example, an April 1992 internal memorandum of Siemens AG ("Seimens ) states that " (a)s a result of the trend toward increasingly faster RISC and CISC processors, the DRA interface has become more and more of a problem for system developers. In order to eliminate this data transmission rate bottleneck, various competing concepts regarding the design of newer DRAs have emerged. . . ." (RX 285A at 1). 37. Similarly, an October 1992 article published in the Institute of Electrical and Electronic Engineers, Inc. ("IEEE") Spectrum warned , " (i)fthe price-to-performance ratio of computer systems is to keep improving, the gap in speed between processors and memory must be closed." (RX 329 at 1). IEEE Spectrum is the overall general magazine for the IEEE, a professional organization of electronic and electrical engineers. (prince, Tr. 8972-73). The article went on to explain that "the accepted dynamic RA (DRA) architectures and solutions have been pushed to their limits. A basic change in architecture seems the only way to obtain an urgently needed increase in memory speed." (RX 329 at 1). This article reflected a general discussion within the industry in 1992 that computer companies needed faster DRAs. (prince Tr. 8977-78). 38. Another article in the October 1992 IEEE Spectrum stated , " (i)f dynamic RAs and processors are to trade data at close to top speed, the interface between them must be reengineered. . . . None of the types of interfaces now popular can do this while conserving power and cost to the desired degree." (R 333 at 1). 39. In February 1994, Dr. Betty Prince, a long-time consultant in the DRA industry and the author of five books on DRA technologies (prince, Tr. 8970-72), wrote in an article published in IEEE Spectrum that " (t)he mismatched bandwidths of fast processors and the slower memory chips they must employ are a problem of long standing. Processors now as always require more data per unit time than many standard memory chips have been designed to provide. " (RX 465 at 1). She also provided a graph showing that this performance gap was increasing over time. (RX 465 at 1). Dr. Prince agreed that the performance gap she wrote about created a bottleneck. (prince, Tr. 8990-91). 40. Intel saw the memory bottleneck coming in 1995 , and the recognition of this bottleneck prompted Intel to investigate various memory technologies in an effort to remedy the situation. (MacWillams, Tr. 4929-30). Farmwald' s and Horowitz s Inventions Solve the Memory Bottleneck Problem by Addressing Numerous Issues 41. In 1988, Dr. Farmwald conceived the general idea of a new memory interface and protocol (an organization of the bits and timing of bits transferred by a memory chip) that would allow a single DRA chip to have higher performance than a board Dr. Farmwald had designed containing 320 existing DRA chips. (Farmwald, Tr. 8086-88). 42. In order to progress beyond his initial ideas Dr. Farmwald realized that he needed the assistance of an expert in circuit design. (Farmwald, Tr. 8089). Dr. Farmwald sought the help of a former colleague - Dr. Mark Horowitz, a professor at Stanford. (Farmwald, Tr. 8089-90). 43. Dr. Horowitz had completed both his bachelors and masters degrees in electrical engineering from MIT in four years, receiving the degrees in 1978. (Horowitz, Tr. 8477). Afer working for a year at Signetics, he then earned a Ph.D. in integrated circuit design from Stanford University in 1983. (Horowitz, Tr. 8477-80). Dr. Horowitz has been a professor in the electrical engineering and computer science departments at Stanford University since the mid- 1980' (Horowitz, Tr. 8476). Dr. Horowitz currently holds two endowed chairs at Stanford. (Horowitz Tr. 8482). 44. Dr. Farmwald convinced Dr. Horowitz to take a year s leave from Stanford to further explore their ideas. (Farmwald, Tr. 8092-93). Starting in the spring of 1989, the two worked from Dr. Horowitz s Palo Alto home. (Farmwald, Tr. 8093-94). 45. Dr. Horowitz s goal was to build the fastest possible DRA interface. (Horowitz Tr. 8486). Drs. Horowitz and Farmwald determined that 500 megahertz ("MH") DRA operation might be possible, and they worked toward that goal. (Horowitz, Tr. 8505-06). 46. In creating their inventions, Drs. Farmwald and Horowitz had to solve numerous problems. (Horowitz, Tr. 8487). They realized that current memory interfaces could not run at high speeds as a result of electrical issues, clocking issues, and issues relating to the protocol, and that they would need innovations in each of these areas in order to meet their goal. (Horowitz Tr. 8487-88). Electrical Issues 47. With respect to electrical issues, Drs. Farmwald and Horowitz needed to develop driver and receiver circuitry that could generate very high-speed signals, and they also needed to develop a bus that would allow the signals to propagate. (Farmwald, Tr. 8118-20; Horowitz Tr. 8488). 48. Drs. Farmwald and Horowitz developed a number of solutions to the electrical issues that arose. First, they realized that reflected signals from the end of the bus lines would be a serious problem at high speeds and conceived the idea of introducing resistors to "terminate" the bus lines and reduce reflections. (Horowitz, Tr. 8492-93). 49. Second, Drs. Farmwald and Horowitz realized that the high voltage signaling then in use would generate too much power at high speeds, and they developed low voltage signaling using a particular kind of driver called a "current mode" or "current source" driver. (Farmwald Tr. 8119, 8144-45; Horowitz, Tr. 8494-95; RX 82 at 9). 50. Third, Drs. Farmwald and Horowitz realized that they could not build a 500 DRA with current technology and so, to transmit data at the highest possible speed, they conceived the idea of transmitting and receiving data on both edges of a 250 MH clock. (Farmwald, Tr. 8118; Horowitz, Tr. 8495-97). Clocking Issues 51. With respect to clocking issues, Drs. Farmwald and Horowitz realized from personal experience that, although current memory chips were asynchronous, they would have to develop a synchronous device with mechanisms for exercising very tight control over timing with respect the clock to make sure that each bit of data - traveling at a very high speed - was sampled at the right time. (Horowitz, Tr. 8488-89; see infra F. 52- , 284 for discussion of asynchronous versus synchronous devices). 52. Drs. Farmwald and Horowitz decided to design a synchronous system since the timing reference provided by a clock could be used to limit timing uncertainties in the system and allow for high speed performance. (Horowitz, Tr. 8499-502). 53. Even in a synchronous system there remain some timing uncertainties; for example expected delays of the buffers may vary from DRA to DRA due to differences in their fabrication. (Horowitz, Tr. 8503-04). In order to have the highest speed possible, Drs. Farmwald and Horowitz wanted to minimize this remaining uncertainty to the extent possible; they therefore came up with the idea of using a delay locked loop (DLL) or a phase locked loop (PLL) on-chip. (Farmwald, Tr. 8118; Horowitz, Tr. 8504). The Memory Interface Protocol 54. With respect to the design of the protocol, additional optimizations developed for high speed operation included returning a variable amount of data in response to a request rather than a single bit of data and by putting registers and associated control circuitry directly on the DRA. (Farmwald, Tr. 8115; Horowitz, Tr. 8489-90). 55. With respect to the protocol, Drs. Farmwald and Horowitz again came up with various innovations. As one example, they decided to put registers on the DRA to make the interface more effcient. (Farmwald, Tr. 8115- 16; Horowitz, Tr. 8506). These registers would be programmed with parameters, such as the address range that a particular DRA would respond to or the access time of the DRA. (Horowitz, Tr. 8507, 8509- 10). 56. Drs. Farmwald and Horowitz wanted to make the access time variable for two reasons. First, if the bus were improved so that it could operate at a faster clock frequency, the access time ofthe DRA could be adjusted so that it would operate with that faster clock. Second, a variable access time would allow the access times of all the DRAs in a system to be adjusted to have the same access time. (Horowitz, Tr. 8510- 11). 57. As another example of an innovation related to the protocol, Drs. Farmwald and Horowitz allowed the response to a request to include a variable amount of data, a feature known as "variable block size" or "variable burst length." (Farmwald, Tr. 8116- , 8146; Horowitz Tr. 8512; RX 82 at 9). ll. RAMBUS: COMPANY DEVELOPMENT AND PUBLIC PROMOTION OF TECHNOLOGY The Founding of Rambus 58. Drs. Farmwald and Horowitz founded "Rambus Inc. " in March of 1990. (CX 545 at 5; RX 81 at 19). By 1992, its headquarters were located in Mountain View, California, in Silicon Valley. (RX 81 at 1, 3). 59. Rambus is, and at all relevant times has been, a corporation as "corporation" is defined by Section 4 ofthe Federal Trade Commssion Act, 15 US. C. ~ 44; and at all relevant times has been and is now engaged in commerce as "commerce" is defined in that same provision. (Answer, ,-,- 5 , 6). 60. Rambus designs, develops, licenses, and markets both nationally and internationally, high-speed chip connection technology to enhance the performance of computers, consumer electronics, and communications systems. (Answer ,- 5). Rambus is a pure-play licensing company; it does not manufacture DRA, but rather uses research and development to invent new DRA technologies and makes its money by licensing its technology to others. (Teece, Tr. 10350-51). 61. For the fiscal year that ended on September 30 2001 , Rambus reported revenues of approximately $117 millon. (Comp. ,- 5; Answer ,- 5). 62. Rambus s founders intended to improve memory performance through multiple inventions based on modifications of standard DRAs (see CX 533 at 2), which could be used separately or in combination(s). The greatest performance gains would be realized by using these inventions in combination. Rambus DRA or "RDRA is the name for the "revolutionary DRA architecture and high speed chip-to-chip data transfer technology" that incorporates several ofRambus s inventions, including its proprietary bus technology. (RX 81 at 3). Each of the various generations ofRDRA are manufactured in accordance with specifications established through a collaboration among Rambus and its DRA partners. (Farmwald Tr. 8149, 8241). 63. Early on, Rambus realized that it was important to its business strategy to protect the intellectual property rights to its technology. (CX 535 at 1). Part of its early strategy to do this was to pursue an application for "a basic, broad patent filed in all major industrial nations" and thereafter "follow up with additional patents on inventions created during the development of the technology. " (CX 535 at 1). It was also important to Rambus to enter into nondisclosure agreements with companies exposed to its technology. (CX 535 at 1). 64. The only business model that "made any sense" to Rambus co-founder Michael Farmwald "was to patent (the technology), convince others to build it, and charge them royalties because "( w )hen we were first formed, it was my view that we could not possibly raise enough money to build DRAs. DRA fabs cost, even back then they cost, (sic) order of a bilion dollars. You couldn t really build DRAs without owning your own fab, and so a business plan which involved actually building and sellng DRAs was hopeless, and so from the very beginnng we were a royalty-based company. " (Farmwald, Tr. 8095; CX 2106 at 27 (Farmwald Dep. )). 65. Rambus s primary objective was to commercialize the revolutionary inventions Drs. Farmwald and Horowitz had created in the form of an open industry de facto standard, and to ensure that the standard "didn t go off in incompatible directions." (Farmwald, Tr. 8110, 8125- , 8148). 66. Rambus contemplated that it would earn its income by working with DRA companies to implement the Rambus interface in their products, and, for that work, get paid consulting fees (for the time its engineers spent working with partners) and royalties for the use of Rambus s intellectual property that would be incorporated into DRA companies' products. (Farmwald, Tr. 8150). 67. To become and remain a viable company, it intended to charge low single digit royalties, which it believed to be fair in light of the importance ofRambus s intellectual property contribution to the product and the large size of the DRA market. (Farmwald, Tr. 8128; Cf( 1282 at 5). 68. Rambus founder Farmwald knew that companies never like to pay royalties unless they have to and they can not "get out of it." (CX 2106 at 27 (Farmwald, Dep. )). Securing Venture Capital Funding 69. In an effort to receive funding for the start-up of Ram bus Inc. , the founders approached various venture capital firms: Kleiner Perkins, one of the largest venture capital firms in the world; Merrill Pickard Anderson and Eyre; and Mohr Davidow. (Farmwald, Tr. 8099). As part of the meetings with the venture capital firms, the founders prepared presentations and showed them documents, such as early business plans. (Farmwald, Tr. 8100). These meetings occurred around the time of a June 1989 RamBus Business Plan. (Farmwald, Tr. 8100-01; see CX 533). 70. The start-up had significant financial considerations and according to the June 1989 business plan , " RamBus" founders (Michael Farmwald, Mark Horowitz), were able to invest $75 000 in "seed money" and were seeking an additional $1.5 millon in equity investment. (CX 533 at 4). This amount would only fund the company through "the completion of a prototype and to the development of (its) initial DRA vendor partnerships. " (CX 533 at 4). Until it signed with its revenue producing partners, estimated expenses were $100 000 per month. (CX 533 at 5). 71. In March 1990, Rambus Inc. was born after receiving venture capital funding of $1. million from three firms. (CX 545 at 5; RX 81 at 19). Early Business Plan for the Farmwald/Horowitz Inventions 72. As a 1989 draft business plan explained, Farmwald and Horowitz hoped to establish a de facto standard "by offering all interested DRA and central processing unit ("CPU") vendors a suffciently low licensing fee (2%) that it wil not be worth their time and effort to attempt to circumvent or violate the patents. " (RX 15 at 9). 73. Dr. Farmwald explained , " (w)e were going to try and find customers for our parts, big customers, and we were going to try and license all the DRA makers to build our part to supply those customers " which would lead to de facto standardization. (Farmwald, Tr. 8124-25). 74. The founders intended to use a program of phased licensing and promotion of its proprietary RDRA technology in order to convince the industry to adopt its proprietary technology as the industry standard. (Farmwald, Tr. 8297). 75. The plan was for their technology to be an "open standard" ; they refused to license its technology on exclusive terms. (Farmwald, Tr. 8185; RX 25 at 16). 76. An "open standard" in the DRA industry is a standard for which any patents that apply to it are available on reasonable and nondiscriminatory terms. (Bechtelsheim, Tr. 5897; CX 2112 at 190-91 (Mooring Dep. )). 77. Farmwald and Horowitz wanted to avoid what happened to the Sony Betamax, which was hampered in the market by restrictive licensing. (Farmwald, Tr. 8165-66). Instead, their goal was to license the technology "openly and fairly to everybody so everyone is on equal footing with a relatively low royalty." (Farmwald, Tr. 8165-66). 78. Their early business plans indicate that they were aware that it would be necessary early on to charge lower royalties in order to foster acceptance of their proprietary technology. They recognized that there was a "trade-off of royalty size vs. incentive to develop alternatives to their technology. (CX 533 at 14). 79. To ensure that the FarmwaldlHorowitz technology was standardized, i. , that parts from one manufacturer were interchangeable with parts from another manufacturer, the inventors planned to cooperate with their partners (i. , the licensees who would manufacture the devices) to ensure that feedback was propagated to all partners so that everyone would use the same good ideas instead of creating customized parts. (F armwald, Tr. 8148; see RX 82 at 17). 80. Farmwald and Horowitz believed that they had compellng, revolutionary ideas, that their patents would be significant, and that a small royalty would be palatable given the performance leap of the technology. (Farmwald, Tr. 8112- 13). 81. . The key to success for F armwald and Horowitz was that they "had to find a number of high-volume customers and high-volume producers to produce the part so that it became the part that everybody was using" in order for their technology to become a de facto standard. (Farmwald, Tr. 8140; CX 1750 at 1). 82. To this end, the inventions were designed to be produced using existing DRA manufacturing technology. (Farmwald, Tr. 8142-43; RX 82 at 6). The RDRAM Technology 83. Because from the start the founders believed that " (rJoyalties are the lifeblood of Rambus" (CX 2106 at 221 (Farmwald, Dep.)), Rambus placed great importance on promoting and protecting its proprietary technology. The Rambus founders "felt we had a very significant invention. We felt that the only way to protect and to extract value from that invention was to patent it." (CX 2106 at 28 (Farmwald, Dep. )). 84. Rambus saw its proprietary Rambus DRA ("RDRA) technology as offering dramatic improvements over existing memory technology of the time. In 1992 it claimed that RDRA technology "achieves a ten-fold increase in component throughput" and would result in dramatically increasing system price/performance." (R 81 at 3). In addition, Rambus claimed that use of the RDRA technology "assures a smaller system with fewer components, and provides the user with a modular, scalable solution. " (RX 81 at 3). 85. The high-speed chip-to-chip data transfer RDRA technology was intended to be used not only in memory chips themselves, but also to be implemented in other chips including memory controllers, processors, graphics/video chips and other high performance components used in virtually every computer system. (RX 81 at 3). The proprietary Rambus technology was targeted at mainstream applications from consumer digital video products to desktop computers and graphics up to massively parallel computers. (R 81 at 3). 86. The RDRA technology in the early 1990' s included numerous inventions relating to the bus, the interface between the bus and computer chips, and the DRA. The 1992 Corporate Backgrounder makes clear that the Rambus "solution is comprised of three main elements: the Rambus Channel, the Rambus Interface, and the RDRA." (RX 81 at 6). The Rambus Channel refers to the bus, while the Rambus Interface and RDRA refer to other Rambus innovations separate from the bus. (RX 81 at 7). Each of these elements contain a number of independent inventions. (RX 81 at 8- 11). 87. RDRA narrow bus technology contemplates the use of circuitry on the chips at either end of the bus connection to optimize the signals flowing across the connection. (Horowitz, Tr. 8488-90). This circuitry contains high-level logic which implements a protocol for the chip-to-chip information transfer. (Horowitz, Tr. 8489-90). 88. One of the ways that RDRA technology achieves a high-speed data transfer over the narrow bus is through "multiplexing, " which means that the bus can carry different pieces of information at different points in time. (Horowitz, Tr. 8620-21). This aspect of the RDRA interface protocol means that over several clock cycles the bus can carry a combination of address and control and data signals on one or more of the same bus lines. (Horowitz, Tr. 8620- 21; see Rhoden, Tr. 402-03). 89. Another aspect of the RDRA technology is the use ofa "packetized" data transfer protocol. (Horowitz, Tr. 8621; Rhoden, Tr. 403-05). This term means that information is bundled and the bundle may be sent over multiple clock cycles rather than transmitted all at once. (Jacob, Tr. 5465; Rhoden, Tr. 403-04). 90. The RDRA technology also contains various other distinctive aspects, including a clocking system, sometimes referred to as a loop clock, to assist in controllng the synchronization of the data transfer between chips (Roden, Tr. 404; Horowitz, Tr. 8647), and a method of physically packaging the RDRA memory chips so that multiple chips could be vertically mounted on one another to occupy a small space. (Horowitz, Tr. 8623). 91. The RDRA technology was suffciently distinctive that it was widely considered revolutionary" in the industry and was promoted as such by Rambus. (Horowitz, Tr. 8571; Gross, Tr. 2291; Heye, Tr. 3686- 87). The 1990 Business Plan 92. Early Rambus investors were informed that "(t)he primary business of the Ramus Company" would be to license proprietary technology "to manufacturers of DRA chips and microprocessors ; that " (t)he DRA market is . . . highly sensitized to the concept of standardization ; and that market conditions were such that there is "the ability to set world wide standards for the next generation of DRA chips and memory systems. " (CX 533 at 9). 93. The purpose of this early draft of its business plan was to encourage investment by explaining to investors why Rambus s technology would enable Rambus to be successful in the existing and future DRA market. (See generally CX 533 at 9- 10). 94. Investors were told that "the patented RamBus technology. . . has the opportunity to establish a single high performance DRA standard " that in part due to " (t)he DRA industry penchent (sic) for standardization " once the Rambus technology was licensed to "all major vendors " it would be "extremely unlikely that any potential competitor would be able to gain critical mass enough to challenge" Rambus; and that such considerations, including the existence of "strong barriers to entry" restraining "potential competitors " made Rambus an "exceptionally attractive investment opportunity. " (CX 533 at 9). 95. The strength ofRambus s business model depended also on the strength of its technological innovations. Indeed, Rambus s early filed broad patent application and the advantage its technology was seen to enjoy by virtue of being "faster, denser, lower power and cheaper than any other approach" were touted to investors as the most significant barriers to entry for potential, follow-on competitors. (CX 533 at 9). It was the "stiff competition" presented by Rambus innovative technology as well as its marketing strategy of licensing all of the major vendors that it claimed made it less pervious to competitors than other potential investment opportunities. (CX 533 at 9). 96. Rambus hired its first (and to date only) Chief Executive Offcer - Geoffey Tatewho joined Rambus in May 1990. (CX 545 at 5). RDRAM Promotion and Licensing Strategy 97. By November 1990, Rambus had begun its efforts to promote and protect its technology. (CX 535 at 4-5). At that date Rambus had filed for, but not yet obtained, a base patent on its technology (CX 535 at 3) and had entered into license contracts that compelled partners to use Rambus technology patents and trade secrets only for use in RDRA-compatible chips. (CX 535 at 4-5). 98. By June 1992, Rambus had signed technology license agreements with NEC Corp. NEC"), Toshiba Corp. ("Toshiba ), and Fujitsu Laboratories, Ltd. ("Fujitsu ). (CX 543A at 11). By January 1994, Rambus had signed license agreements with Hitachi, Ltd. ("Hitachi"), Oki Electric Industry Co. ("Oki"), Lucky Goldstar, and Intel. (CX 547 at 12). These agreements involved substantial interaction between Rambus and the licensees. (Farmwald, Tr. 8241). 99. In the course of negotiating with DRA manufacturers and others, Rambus encountered resistence to its business model, and specifically to royalties. (CX 711 at 13 , 61). A few systems companies and IC (integrated circuit) companies have had a very negative reaction to our business model. Some believe that it is not ' fair' that we are wanting to charge a royalty on ICs that incorporate our technology. Others believe our royalty wil make ICS incorporating our technology ' too expensive. ' Two specific examples are Sun and Tseng. (CX 543A at 14). 100. Rambus limited the use of its license agreements to so-called RDRA compatible uses only. Most companies accepted this term. Samsung Electronics Co. , Ltd. ("Samsung however, insisted on an agreement without field of use restrictions. (CX 767). 101. In 1994, Samsung recognized that Rambus s inventions could be used in noncompatible Rambus parts, i.e. in parts without Rambus s proprietary bus technology. (CX 767). Moreover, Rambus made it clear to Samsung that Rambus s intellectual property rights were not limited to the RDRA product. (CX 2078 at 116 (Karp, Dep. )). Presentation of the Rambus Inventions to the DRAM Industry Rambus Visits to DRAM Manufacturers and Systems Companies 102. In 1989- , Drs. Farmwald and Horowitz made visits to many DRA manufacturers and systems companies to try to convince them about the benefits of their approach and to get feedback from them. (Horowitz, Tr. 8515). 103. Among the DRA manufacturers that Drs. Farwald and Horowitz visited in 1989- 90 were Texas Instruments, ffM, Toshiba, Fujitsu, Mitsubishi Electric Corp. ("Mitsubishi" NEC, Matsushita Elect. Indus. Co. , Ltd. ("Matsushita ), Micron, and Siemens (whose former semiconductor division is now Infneon Technologies). (Horowitz, Tr. 8515; Farmwald Tr. 8166). 104. Among the systems companies that Drs. Farmwald and Horowitz visited in 1989- were ffM (both a DRA manufacturer and a systems company), Sun Microsystems ("Sun Motorola, Apple Computer ("Apple ), SGI, and Tandem. (Horowitz, Tr. 8515; Farmwald Tr. 8166-67). 105. The response to the early presentations in 1989-90 was "just disbelief' that Drs. Farmwald and Horowitz would be able to achieve a 500 megabit per second DRA data rate. (Horowitz, Tr. 8516). People who listened to these presentations were also skeptical about many ofthe specific features of the technology. For example, it was felt that putting registers on DRA was too expensive for a commodity part and that one could not put a phase locked loop or a delay locked loop on the DRA itself (Horowitz, Tr. 8517). 106. The four inventions at issue in this case were described in these early presentations. For example, one of the early presentations that Dr. Horowitz gave, with slides dated January 31 1990, states that the Rambus interface "allows ' block mode' transfer from an individual DRA with " 1024 byte long blocks supported." (R 29 at 9; Horowitz, Tr. 8518-20). This describes variable block size or variable burst length. (Horowitz, Tr. 8520). 107. The January 31 , 1990 presentation also describes the use of a delay locked loop on the DRA to reduce clock skew. (RX 29 at 33-34; Horowitz, Tr. 8521-22). 108. The January 31 , 1990 presentation also refers to the dual-edge clock or double data rate technque. (RX 29 at 34; Horowitz, Tr. 8522-23). Preparation and Description of the Rambus Inventions Through Various Technical Publications 109. In the 1990-91 period, Dr. Horowitz prepared detailed techncal descriptions of the Rambus technology. (Horowitz, Tr. 8523). These documents were for Rambus s internal use and were also used with customers and potential customers to convince them of the merits of Rambus technology and to help them build it. (Horowitz, Tr. 8523-24). These documents disclose all four ofthe relevant product markets in this case: dual-edge clocking, on-chip DLL programmable CAS latency, and programmable burst length. The May 1990 Technical Description 110. One ofthese techncal descriptions is dated May 7, 1990 and was generated at about that time. (R 63; Farmwald, Tr. 8168-69; Horowitz, Tr. 8524-25). 111. The May 7, 1990 techncal description described all four of the technological features at issue in this case. (Horowitz, Tr. 8525-29). 112. For example, the techncal description described dual-edge clocking in a figure with two input receivers, one clocked by a signal designated "CLK" (clock) and the other clocked by the complement ofCLK (clock bar), a signal that is zero when clock is one and vice versa. (R 63 at 10; Horowitz, Tr. 8525-26). This means that one receiver samples an input when the clock goes high (the rising edge of the clock) and the other when the clock goes low (the fallng edge). (Horowitz, Tr. 8526). 113. The May 7, 1990 techncal description also described a delay-locked loop on the DRA (on-chip DLL feature). (Horowitz, Tr. 8527-28). A figure in the techncal description shows two delay locked loops generating the internal clocks for Rambus s design. (R 63 at 14; Horowitz, Tr. 8527). 114. The May 7, 1990 techncal description also described programmable latency. (Horowitz, Tr. 8528). In the "device registers" section of the document, an "access time" or latency register is listed. (RX 63 at 18; Horowitz, Tr. 8528). "Latency" refers to the time between request and response. (Horowitz, Tr. 8530). The document explains that a fixed value for latency "does not allow for technology improvements " and, consequently, the Rambus system set(s) the time between request and response during system reset." (RX 63 at 5-6; Horowitz Tr. 8530-31). In other words, the value in the access time or latency register would be fixed when the system was started up and probably would not be changed after that time. (Horowitz Tr. 8531). 115. The May 7, 1990 techncal description also described variable burst length. (Horowitz, Tr. 8528-29). The document contains a table showing a variable number of bytes in the block size or burst length depending on the value in the "BlockType" field. (RX 63 at 21; Horowitz, Tr. 8528-29). The November 1990 Technical Description 116. A later Rambus techncal description, dated November 5, 1990, was generated around that time. (R 94; Farmwald, Tr. 8169; Horowitz, Tr. 8535) 117. The November 5, 1990 techncal description was sent to Siemens (now Infneon). (R 99; Farmwald, Tr. 8169-70). 118. The November 5, 1990 techncal description described dual-edged clocking. First the document contains the same figure relating to inputting data on both edges of the clock as in the May 7, 1990 description. (R 63 at 10; RX 94 at 15; Horowitz, Tr. at 8535-36). Second the document shows that the output data is also being transmitted on both edges of the clock. (R 94 at 19; Horowitz, Tr. 8536). 119. The November 5, 1990 techncal description described two alternatives for the DRA clock circuitry. One alternative was to use a phase locked loop. (RX 94 at 45; Horowitz Tr. 8536-37). The other alternative was to use delay locked loops. (R 94 at 46; Horowitz Tr. 8537). 120. The November 5, 1990 techncal description described varable latency using a data delay field in the request packet. (R 94 at 59; Horowitz, Tr. 8537-38). 121. The November 5, 1990 techncal description described variable block size or burst length with a table similar to that in the May 7, 1990 techncal description. (RX 63 at 21; RX 94 at 60; Horowitz, Tr. at 8538). Siemens Responds With a List of Questions About Rambus Technology 122. Both Dr. Farmwald and Dr. Horowitz received feedback from Siemens regarding the November 5 1990 techncal description. (R 102; RX 117; Farmwald, Tr. 8171-72; Horowitz Tr. 8541-42). 123. A fax from K. Horninger of Siemens to Dr. Farmwald, dated December 7, 1990 contained a detailed list of questions relating to the November 5 , 1990 techncal description. 102; Farmwald, Tr. 8171-73). 124. A fax from H.1. Neubauer of Siemens to Dr. Horowitz, dated January 29, 1991 stated "Dear Dr. Horowitz, concerning the RAUS Techncal Description some basic items remained open. In the following we present a list of detailed questions to you which we would like to get answered." (R 117 at 2; Horowitz, Tr. 8542). 125. A number of the questions in the fax that Siemens sent to Dr. Horowitz related to the four features of Ram bus technology at issue in this case. (See RX 117). 126. Question number one in the Siemens fax asked about the details of how eight bits of data would be transmitted by the DRA and relates to Rambus s variable block size feature. (RX 117 at 2; Horowitz, Tr. 8543-44). 127. Question number two in the Siemens fax asked about the implementation of variable latency in the Rambus technology. (R 117 at 2; Horowitz, Tr. 8544). 128. Another question in the Siemens fax referenced Figure 13 on internal page 14 of the November 5, 1990 techncal description. (R 117 at 4). That figure showed dual-edge clocking or double data rate on the output. Dr. Horowitz s understanding was that Siemens s question related to the implementation ofthe double data rate drivers as shown in the November 5, 1990 techncal description. (R 94 at 19; RX 117 at 4; Horowitz, Tr. 8546). 129. Another question in the Siemens fax referenced Figure 28 on internal page 41 ofthe November 5, 1990 techncal description. (RX 117 at 4). That figure shows a delay locked loop and Siemens s question was about the delay locked loop. (RX 94 at 46; RX 117 at 4; Horowitz Tr. 8546). The April 1991 Technical Description 130. A stil later Rambus techncal description was released on April 1 , 1991 and was a more complete version with many more techncal details. (R 130; Farmwald, Tr. 8171; Horowitz, Tr. 8538). 131. The April 1 , 1991 techncal description described dual-edged clocking. (R 130 at 36; Horowitz, Tr. at 8539). 132. The April 1 , 1991 techncal description described using a phase locked loop on the DRA. (RX 130 at 56; Horowitz, Tr. 8539). 133. The April 1 , 1991 techncal description described programmable latency through the use of a "read delay" or latency register. (RX 130 at 94; Horowitz, Tr. 8539-40). 134. The April 1 , 1991 techncal description described variable block size or burst length with the value in a "count" field representing the number of bytes to be transferred. (R 130 at 64; Horowitz, Tr. at 8539). The March 1992 Press Events 135. On March 9, 1992, Rambus held simultaneous events in the Silicon Valley and in Tokyo to publicly announce its technology and its business plan. (Farmwald, Tr. 8182-84; RX 67 at 1). Prior to this date, Rambus had presented its technology to companies on an individual basis and had secured licenses from three ofthe top five DRA manufacturers: Fujitsu, NEC, and Toshiba. (RX 67 at 2). 136. The press release announcing these events stated that Rambus s revolutionary technology would offer a tenfold improvement over traditional DRAs and would solve the memory bottleneck. (R 67 at 1). The press release also described Rambus s business plan as licensing its technology in return for license fees and royalties. (R 67 at 2). By controllng the Rambus interface standard, Rambus would ensure compatibility. (R 67 at 2). The press release also made it clear that Rambus s "open standard" would be "available for license by any IC (Integrated Circuit) company." (R 67 at 2; see also Farmwald, Tr. 8185). 137. At the events, Rambus made available a "Corporate Backgrounder" that provided an overview ofRambus s business strategy and its technology. (R 81; Farmwald, Tr. 8186). The Backgrounder explicitly detailed Rambus s intellectual property strategy: "Rambus Inc. is fully protecting the intellectual property rights of its technology by filing basic, broad patents in all major industrial nations around the world." (RX 81 at 3). 138. Later in this same public document, there are descriptions ofRambus s technology. (R 81 at 8- 11). The Backgrounder states that Rambus s "dramatic performance improvements were achieved through numerous techncal breakthroughs" and then proceeds to describe " (s)ome of the major techncal higWights of the Rambus solution. " (RX 81 at 8). The technology descriptions included the use of dual-edge clocking: " (a)n innovative electrical interface permits the Rambus Channel to operate at 500 Megabytes/second by using both edges of a 250 clock." (RX 81 at 8). Moreover, the technology descriptions explicitly state that Rambus used the on-chip PLL/DLL technology: "(c)lock skew and capacitive loading are minimized by a phase lock loop circuit on board both the master and the RDRA." (R 81 at 8). 139. The Backgrounder also made it clear that Rambus s technology was divided into three distinct elements of the memory system: the Rambus Channel (the high-speed bus); the Rambus Interface (the circuitry that connects a device, such as a controller or DRA, to the bus); and the Rambus DRA (the memory itself). (RX 81 at 7; Farmwald, Tr. 8188-90). 140. The Backgrounder also stated that Rambus s business strategy was to license its technology, work with the licensee to help implement the technology, and to receive fees and royalties in return. (R 81 at 3; see also Farmwald, Tr. 8186-87). 141. Later that year, at the invitation of Betty Prince, a long-time consultant in the DRA industry (prince, Tr. 8970- , 8986-87), Dr. Farmwald and David Mooring of Ram bus published an article in the October 1992 issue of IEEE Spectrum, which gave a brief description of the Rambus technology and stated that the "technology behind the architecture can be licensed for a royalty fee comparable to that for other patented technologies." (R 332 at 1). 142. During the early 1990' s Rambus s business model was well known in the industry. Brett Willams, a JEDEC Solid State Technology Association ("JEDEC") representative for Micron testified that in 1992 , " I knew it was (Rambus sJ business model to patent their technology, and that's how they would gain their revenues. " (Wiliams, Tr. 857). Similarly, Martin Peisl ofInfneon stated that he was aware ofRambus s business model in the early 1990' and expected Rambus to get patents to cover its technology. (Peisl, Tr. 4505). 143. According to Andreas Bechtelsheim, formerly of Sun Microsystems, Rambus made very clear to Sun that it intended to seek patent coverage for all of its inventions and developments, and Rambus explained to various companies, including Sun, that it was seeking patent coverage for its inventions because it intended to obtain revenue or earn revenue through licensing its technology to both memory manufacturers and system manufacturers. (Bechtelsheim Tr. 5819). Press Coverage: The March 1992 Microprocessor Report Article 144. In connection with the public announcement ofRambus s technology and its business plan in March 1992, Rambus provided information to the press regarding Rambus inventions, and numerous articles about Rambus appeared. (RX 1446). 145. Many ofthese articles provided a significant amount of techncal detail. For example, an article entitled "Rambus Unveils Revolutionary Memory Interface" in the March 4 1992 Microprocessor Report describes Rambus s technology in some depth and described three of the four features of Ram bus technology at issue here, as well as aspects of the fourth. (RX 1446 at 22-26). 146. The article states thatthe "Rambus Channel is a 500-Mbyte/s interface, operating with a 250-MH clock and transferring a byte of data on each clock edge" and that a "phaselocked loop on each Rambus device limits clock skew within the chip." (R 1446 at 22 23). 147. The article also states that the "six-byte request packet encodes a 36-bit address, a bit operation code, and 8-bit transfer length count (in bytes). Byte addressing and block sizes of up to 256 bytes are supported." (RX 1446 at 24). 148. The article also notes that "control registers" on the DRA can be used to specify certain parameters. (R 1446 at 23). Rambus s Disclosure of Inventions Through Public Documents The 1992 Marketing Brochure 149. In early 1992, Rambus produced and distributed its first marketing brochure about Rambus technology. (RX 2183; Horowitz, Tr. 8547). The 1992 marketing brochure describes the four features of Ram bus technology at issue here. (Horowitz, Tr. 8547-48). 150. The 1992 marketing brochure states that the "heart of (the Rambus) Interface is high performance PLL (phase-locked-loop) circuitry which provides the clocks for transmitting and receiving Rambus Channel data. " (RX 2183 at 6). 151. The 1992 marketing brochure describes variable burst length, because data transfers could involve a variable amount of data, indicating: " (t)ransfers of 1 to 256 Bytes per Request." (R 2183 at 7). 152. The 1992 marketing brochure describes dual-edge clocking, stating that " ( d)ata effectively transferred on both edges of the clock." (R 2183 at 9). 153. The 1992 marketing brochure describes programmable latency, stating that "the Read Data Packet is returned a time ReadDelay after the Request Packet" and that this delay value is "programmed into the confguration registers of all devices during system initialization. (R 2183 at 11). Publications Describing the First Rambus DRAM 154. The first Rambus DRA was a 4. 5 megabit Rambus DRA produced by Toshiba in the 1991-92 time frame. (Horowitz, Tr. 8548-49). 155. A paper about the Toshiba 4. 5 megabit Rambus DRA was presented at the 1992 Iriternational Symposium on VLSI Circuits (VLSI Circuits Symposium) and published in the proceedings of that symposium. (R 301 at 76-77; Horowitz, Tr. 8552-54). 156. The VLSI Circuits Symposium is held annually and is one of the top two conferences in the world for circuit designers. (Horowitz, Tr. 8552). The "techncal program commttees" of the Symposium read all the papers submitted and choose the better ones for publication at the conference. (Horowitz, Tr. 8552-53). The techncal program commttees for the 1992 VLSI Circuits Symposium that selected the paper about the Toshiba 4. 5 megabit Rambus DRA included representatives from ffM; Texas Instruments; Siemens AG; Sun Microsystems; Intel; Hitachi; Samsung; Matsushita; Mitsubishi; Fujitsu Laboratories, Ltd. ; Sanyo Electric Co. , Ltd. ; Oki; and NEC. (RX 301 at 5). 157. The paper published in the proceedings of the 1992 VLSI Circuits Symposium about the Toshiba 4. 5 megabit Rambus DRA discusses the four features of Ram bus technology at issue in this case. (Horowitz, Tr. 8554). Figure 2 of the paper shows a block size transfer and read latency. (RX 301 at 77; Horowitz, Tr. 8555). Figure 3 of the paper shows double data rate input receivers. (RX 301 at 77; Horowitz, Tr. 8555). The paper also states that " (t)o eliminate skew caused by the internal circuitry, the DRA contains two PLLs." (RX 301 at 76; Horowitz Tr. 8555). 158. At the end of the 1992 VLSI Circuits Symposium, the authors of the top papers were invited to provide a longer version to be published in the Journal of Solid State Circuits. (Horowitz, Tr. 8555-56). The Journal of Solid State Circuits is the most widely read journal for circuit designers. (Horowitz, Tr. 8555-56). The paper about the Toshiba 4. 5 megabit Rambus DRA was selected, and a longer version of that paper was published in the Journal of Solid State Circuits in April 1993. (R 385; Horowitz, Tr. 8556). Presentations of the Proprietary RDRAM Technology and Nondisclosure Agreements 159. Continuing for many years, Rambus pursued a strategy of actively promoting its proprietary RDRA technology to companies that were in a position to manufacture memory chips or related chipsets. Rambus also promoted RDRA to others, including systems companies. (See Crisp, Tr. 2931; CX 543A at 1 , 3 , 7-8). 160. Rambus s efforts to promote adoption of its proprietary RDRA technology included making presentations concerning the proprietary RDRA technology to memory chip manufacturers and other firms. (E.g. CX 2107 at 63 (Oh, Dep.); Bechtelsheim, Tr. 5818- 19; Kellogg, Tr. 5052-53). 161. In connection with such efforts, Rambus commonly entered into nondisclosure agreements that prohibited the firms from disclosing information concerning the proprietary Rambus technology to others without the consent of Ram bus. (Bechtelsheim, Tr. 5818- 19; Rhoden, Tr. 521; Kellogg, Tr. 5052-53). Rambus s presentations often included a discussion of the patent protection Rambus was seeking for its inventions. (CX 2079 at 83 (Mooring, Dep. CX 2111 at 314- 316- 319- , 320- , 322-24 (Tate, Dep. )). 162. In April 1992, Gordon Kelley offfM attended a presentation by Rambus at ffM comparing the proprietary Rambus RDRA technology with Synchronous Dynamic Random Access Memory ("SDRA). (G. Kelley, Tr. 2535). 163. Desi Rhoden was employed at Hewlett-Packard ("HP") when he began to learn about the Rambus technology in the early 90's. (Roden, Tr. 396). Rambus came to HP to give a presentation about its new memory that it was developing. (Rhoden, Tr. 396). The presentation was made pursuant to a nondisclosure agreement between Rambus and HP. (Rhoden, Tr. 521). Although Rambus did not say anything at that presentation about pending Rambus patent applications, Rhoden assumed that Rambus probably did have patent applications. (Roden, Tr. 521). 164. Andreas Bechtelsheim, a Vice-President for technology at Sun (Bechtelsheim, Tr. 5752), was involved in presentations and discussions with Rambus and understood that Rambus had patent rights that covered its proprietary RDRA technology. (Bechtelsheim, Tr. 5828-29; 5841-42). Rambus "made clear (to Bechtelsheim) that they were going to protect any patent on their memory technology because that was their business model." (Bechtelsheim, Tr. 5829). 165. Mark Kellogg, an employee offfM, learned about Rambus technology through a presentation by Rambus to ffM in the early 1990's. (Kellogg, Tr. 5017, 5052-53). 166. Terry Lee, an employee at Micron, learned about Rambus technology in part from a meeting with Rambus held in 1995. (Lee, Tr. 6601-02). Following the meeting, he and a colleague, Kevin Ryan, reviewed selected patent abstracts. (Lee, Tr. at 6607-08). Lee concluded that the patents appeared to apply specifically to the RDRA bus structure. (Lee, Tr. at 6610- 11). In March of 1997, Lee expressed concerns to the JEDEC JC 42. 3 commttee that a double data rate SDRA ("DDR SDRA) presentation "looked like" one of the Rambus patents he had reviewed in 1995. (Lee, Tr. 6956-59). The June 1992 Business Plan 167. By June 1992, Rambus CEO Geoffey Tate transmitted to the Rambus Board of Directors a comprehensive five-year business plan, which, he explained, was based on "inputs from all of the executives." (CX 543A at 1). As reflected in the "Executive Summary" of this June 1992 Business Plan, Rambus s strategy was to: develop a breakthrough technology with high value added in a large percentage of computer, communications, and consumer digital systems products; establish strong intellectual property barriers; . . . to license the technology for integration onto high volume ICs of all major IC companies and to have license fees cover the costs of technology and market development; to establish Rambusas the new interface standard for systems requiring high performance at low cost; . . . to establish a very high profit stream of technology royalties; (and) to continually improve on Rambus Technology through minor and major enhancements. . . . (CX 543A at 3). Rambus Patent Applications The ' 898 Patent Application 168. Rambus filed patent application serial no. 07/510 898 (the ' 898 application) in the United States Patent and Trademark Offce ("PTO") on April 18, 1990. (CX 1451 at 1- Nusbaum, Tr. 1507). The ' 898 patent application included a descriptive portion, called the specification " that was sixty-two pages long, and included fifteen original drawings. (CX 1451 at 3- , 140-50). The ' 898 patent application contained one-hundred fifty claims. (CX 1451 at 64- 125). 169. In connection with the prosecution of its ' 898 patent application, Rambus was issued a communication by the patent examiner at the PTO containing a restriction requirement. (Nusbaum, Tr. 1511). 170. A restriction requirement reflects that the examiner has reviewed the application and determned that the application contains claims describing multiple "independent and distinct inventions. " The applicant is required to elect which of the claimed inventions it wishes to pursue in the application. (Nusbaum, Tr. 1510). 171. The restriction requirement received by Rambus was an eleven-way restriction requirement; Rambus responded by restricting its original application and filing ten divisional patent applications on March 5, 1992, all of which claimed priority based on the filing date of the original ' 898 application, April 18, 1990. (Nusbaum, Tr. 1511- 12; First Set of Stipulations, Stip. 22). 172. Over time, Rambus filed numerous additional continuation and divisional patent applications claiming priority based on the filing date ofthe original ' 898 application. (See First Set of Stipulations, Stip. 22). 173. Prior to June 1996, Rambus filed a total of seventeen continuation and divisional patent applications claiming priority based on the filing date of the original ' 898 application, and had been issued six United States patents on such applications. (First Set of Stipulations, Stip. 22). 174. As of April 2003 , Rambus had fied sixty-three continuation and divisional patent applications claiming priority based on the filing date of the original ' 898 application, of which ten were stil pending. (First Set of Stipulations, Stip. 22). 175. As of April 2003 , at least 43 United States patents had been issued to Rambus from continuation and divisional applications claiming priority to the original ' 898 application. (First Set of Stipulations, Stip. 13). 176. Over time, various of the Rambus continuation and divisional patent applications claiming priority to the ' 898 application embodied changes and amendments to the claims made in the original ' 898 application and came to describe aspects of the original invention. (See, e. Crisp, Tr. 2927-28). 177. The patents that Rambus has asserted against DRA manufacturers have all issued from applications that are continuations or divisionals stemmng from the original ' 898 application and all share a specification with that original application. (First Set of Stipulations, Stip. 22; Nusbaum, Tr. 1513- 14). 178. Pursuant to the "written description" requirement for a patent's validity, the PTO determned that the claims of these patents were supported by the specification of the original 898 application. (Nusbaum, Tr. 1611- 14). The ' 703 Patent 179. Rambus s first United States patent, US. Patent No. 5 243 703 ("the ' 703 patent" issued on September 7, 1993. (RX 425). Rambus disclosed the ' 703 patent to JEDEC during a commttee meeting in September 1993. (First Set of Stipulations, Stip. 11). The ' 703 patent was subsequently added to the "patent tracking list" maintained by JEDEC, where it was described as involving a "Sync Clock." (JX 18 at 18). 180. The ' 703 patent can be traced back to a divisional application of the original ' 898 application. (R 425 at 1; Fliesler, Tr. 8812). 181. The written description and drawings of the ' 703 patent, like all the issued patents that claim priority to the ' 898 application, are substantially the same as the wrtten description and drawings in the ' 898 application. (RX 425 at 1; CX 1451 at 1; Fliesler, Tr. 8812 8817). Thus the ' 703 patent contains the same descriptions oftechnologies as in the ' 898 application and PCT application. (RX 425 at 7, 8, 9, 14- 21; Fliesler, Tr. 8819-20). 182. In addition to listing the original ' 898 application, the ' 703 patent's written description also contains a list ofthe nine other divisional applications stemmng from the ' 898 application that were pending at the time. (R 425 at 11; Fliesler, Tr. 8813- 14). The PCT Application 183. On April 16, 1991 , Rambus filed an international patent application pursuant to the Patent Cooperation Treaty (the "PCT application ). (CX 1454 at 1). 184. The PCT application is identical in all material respects to the ' 898 application. In particular, the PCT application contains the same written description, drawings, and claims as the 898 application. (CX 1451; CX 1454; Fliesler, Tr. 8811). 185. The PCT application was published and made publicly available as of October 31 1991. (CX 1454 at 1; First Set of Stipulations, Stip. 8). Several JEDEC members obtained the PCT application in the early 1990' , including Mitsubishi and ffM. (R 379A at 1; RX 201 at 1). The ' 898 and PCT Applications Describe Numerous Inventions 186. The ' 898 and PCT applications each contain a lengthy disclosure consisting of a sixty-two page written description, fifteen drawings, and one hundred and fifty claims. (CX 1451 CX 1454). 187. The written description of the ' 898 and PCT applications contain numerous headings and subheadings, such as "Device Address Mapping, " " Bus " " Protocol and Bus Operation Retry Format " " Bus Arbitration " " System Confguration/eset " " ECC " " Low Power 3- Packaging, " " Bus Electrical Description " " Clocking, " " Device Interface " " Electrical Interface - Input/Output Circuitry," and "DRA Column Access Modification." (CX 1451 at 18 , 32, 37, 40, 43 , 45 , 47, 54; CX 1454 at 18 , 55). 188. Although the applications describe how an entire system is to be put together, they also describe numerous techncal features that can be used independently of one another and of the system. (Fliesler, Tr. 8788-89). 189. The ' 898 and PCT applications note that, although a preferred implementation ofthe invention contains 8 bus data lines , " (p)ersons skilled in the art wil recognize that 16 bus data lines or other numbers of bus data lines can be used to implement the teaching of this invention. (CX 1451 at 10; CX 1454 at 10). 190. A person of ordinary skill in the art to which the ' 898 and PCT applications pertain would have an electrical engineering degree and at least two to three years of experience in designing computer memory circuits. (Fliesler, Tr. 8779-80; Nusbaum, Tr. 1613). 191. It was Dr. Horowitz s understanding when the patent application was filed that the various solutions to problems described in the application could be used independently of one another. Thus, if one did not want quite the level of performance that Drs. Farmwald and Horowitz envisioned, one could use only a subset of the technques described in the patent application. (Horowitz, Tr. 8514- 15). 192. Dr. Farmwald never thought of his ideas as implementing a "narrow" bus. (Farmwald, Tr. 8143). Rambus originally used a 9-bit wide bus because that corresponded to the number of pins that could fit on the edges of the chips that existed at the time; later Rambus used wider buses because more pins could be placed on the chip. (Farmwald, Tr. 8143-44). Whle some ofthe inventions ofDrs. Farmwald and Horowitz might enable narrower busses to work better, the inventions are not specific to a particular bus width. (Farmwald, Tr. 8144). 193. A March 12, 1993 Mitsubishi memorandum begins by stating that a "need has arisen to evaluate in detail all of the claims in a patent being applied for by Rambus (1 patent, a total number of claims is 150)." (R 2214A at 1). The memorandum goes on to list guidelines for this evaluation, including " 1) Do not discuss Rambus interface. 2) Determne whether or not any other areas contain technologies that wil be important in increasing memory speed in the future. (RX 2214A at 1). 194. A June 10, 1993 Mitsubishi document with the heading "RAUS Patent (summary of responses)" states: " (i)n addition to the technologies of narrower bus width and communication by protocol that are described above, the RAUS patent includes a variety of requirements such as memory system confguration, packaging method, and device confguration and it can be achieved through a combination ofthese factors." (R 406 at 4). The document continues: "(t)he individual technologies that appear in the RAUS patent wil be used independently in the future." (R 406 at 4). Description of Access Time Registers 195. The ' 898 application and the PCT application describe access time registers that store latency, that is the amount oftime between receiving a request and driving data onto the bus in response to that request. (CX 1451 at 16 23; CX 1454 at 16 23; Jacob, Tr. 5481). The applications state that "(e)ach slave may have one or several access-time registers " where "slave can refer to a DRA. (CX 1451 at 16; CX 1454 at 16; Jacob, Tr. 5649). 196. In common use, programmable CAS latency in the mode register of an SDRA is set at initialization. (Jacob, Tr. 5648-49). The ' 898 application and PCT application state with respect to the access time registers (and other registers): " (m)ost of these registers can be modified and preferably are set as part of an initialization sequence." (CX 1451 at 16; CX 1454 at 16). 197. A Mitsubishi document headed "Assessment of Ram bus Patents (Second Half)" states next to the numbers 95 97 and 103: "Modifiable Access Time Register (Similar to SDRA latency control)." (RX 2213A at 25 27). Claim 103 of the PCT application (and ' 898 application) refers to a "modifiable access-time register." (CX 1451 at 104; CX 1454 at 105). 198. In a claim-by-claim analysis of the PCT application produced by Mitsubishi, a marginal note identifies claim 103 of the application as relating to latency and SDRA. (RX 2213A at 7, 9). The analysis further indicates that Mitsubishi determined that this claim relating to latency in SDRAs was particularly important, for Claim 103 was marked "A." (RX 2213A at 7, 9). A later page of the document explains that an "A" grade means that a technology is "important for increasing DRA speed." (RX 2213A at 27). Description of Block Size 199. The ' 898 application and the PCT application describe varying the "block size " that is the amount of data transmitted in response or received in response to a request. (CX 1451 at 29-30; CX 1454 at 29-30; Jacob, Tr. 5477-78). The applications each state that "BlockSize (0:3) specifies the size of the data block transfer. " (CX 1451 at 29; CX 1454 at 29). The applications each contain a table showing the "Number of Bytes in Block" corresponding to the value in the BlockSize" field. (CX 1451 at 30; CX 1454 at 30). 200. "Burst length " as the term is used in SDRAs, refers to the amount of data to be transferred per read or write transaction. (Rhoden, Tr. 379-80; Jacob, Tr. 5396-97.) Likewise block size " encodes the amount of data to be transferred per read or write transaction. (Jacob Tr. 5477). The two terms describe the same function and are used interchangably. (Horowitz Tr. 8661-62; Geilhufe, Tr. 9643). Description of Bus Clock 201. The ' 898 and PCT applications state: " (c)lock distribution problems can be further reduced by using a bus clock and device clock rate equal to the bus cycle data rate divided by two, that is, the bus clock period is twice the bus cycle period. Thus, a 500 MH bus preferably uses a 250 MH clock rate." (CX 1451 at 49; CX 1454 at 50). If clock rate is half the data rate on the bus, both edges of the clock must be used to transmit data. (Fliesler, Tr. 8801-02). 202. Figure 10 in the ' 898 and PCT applications shows two input receivers clocked by clock" and "clock bar" as in the Rambus techncal descriptions. (CX 1451 at 147; CX 1454 at 148; Fliesler, Tr. 8799). If "clock bar" is high when "clock" is low, and vice versa, data is input on both the rising and fallng edges of clock. (Fliesler, Tr. 8799-800). 203. Figure 13 in the ' 898 and PCT applications shows a timing diagram with data being input, as indicated by the arrows along the bottom of the figure, on both the rising and fallng edges of the clock. (CX 1451 at 149; CX 1454 at 150). Howard Sussman, the JEDEC representative for Sanyo and formerly the JEDEC representative ofNEC, testified that Figure 13 of the PCT application shows to him that "input being sampled on the high and low edge of the clock" and that is "double data rate input." (Sussman, Tr. 1322, 1467-68). Description of Variable Delay Circuitry With a Feedback Loop 204. Figure 12 ofthe ' 898 and PCT applications describes variable delay circuitry and a feedback loop. (CX 1451 at 148; CX 1454 at 149; Jacob, Tr. 5649-50). 205. When Joel Karp, then of Sam sung, reviewed Rambus s PCT application in 1991 Figure 12 'jumped out" at him as evidencing a DLL. (CX 2078 at 119 (Karp Micron Dep. CX 2114 at 276-77 (Karp Dep. 206. In its license negotiations with Rambus in 1994, Joel Karp felt that Samsung was motivated to seek a non-assertion provision for non-Rambus-compatible uses ofRambus inventions because of the on-chip DLL shown in Rambus s PCT application. (CX 2078 at 107- , 119-20 (Karp, Micron Dep. )). Review of the ' 898 or PCT Application Should Have Raised Concerns That Rambus Might Be Able to Obtain Claims Over the Four Technologies at Issue 207. A person of ordinary skill in the art or a patent lawyer reviewing the ' 898 application or PCT application would have realized that Rambus might have claims broad enough to cover programmable CAS latency, programmable burst length, dual-edge clocking, and on-chip DLL. (Fliesler, Tr. 8784- , 8810- 11). 208. An experienced DRA designer reviewing the PCT application would reach the conclusion that there is considerable similarity in form and function between programmable latency, variable burst length, dual-edge clocking, and on-chip DLL as described in the PCT application and the corresponding features in SDRAs or DDR SDRAs. (Geilhufe, Tr. 9556- 57). 209. If an experienced DRA designer working on designing an SDRA incorporating programmable latency and burst length in the early 1990's had reviewed the PCT application, he likely would have become concerned that Rambus might have claims to those features and would have raised the issue with management. (Geilhufe, Tr. 9558). 210. A manager faced with this issue, in light of the potential for substantial economic consequences if a DRA design infnges a patent, would likely have gathered additional techncal analysis from specialists and, if there remained a concern, would have taken the issue to corporate counsel for a careful review. (Geilhufe, Tr. 9558-59). 211. When Mitsubishi reviewed the PCT application, it undertook an in-depth study. A March 3 , 1993 Mitsubishi memorandum requests cooperation on evaluating Rambus s PCT patent application because they "realized that the technology is related not only to stand-alone semiconductor devices but also to systems." (R 379A at 1). 212. A June 10, 1993 Mitsubishi document stressed the need for expert analysis of Rambus s patent application to determine the scope of the claims, particularly as to individual technologies disclosed in the patent application: " (t)here is a need to examine the specifications of the patent claims to determine whether individual technologies used independently will infinge on the RAUS patent, and for that we wil have to obtain the views and interpretations of experts. " (RX 406 at 4; see also RX 416A at 1). 213. An August 16, 1993 Mitsubishi document again raised the issue of whether Rambus could have claims on features separate from any particular bus architecture. (RX 419A at 1). 214. A January 11 , 1996 memorandum indicates that Mitsubishi subsequently conducted an "investigation of the US patents owned by Rambus" that were granted by the end of October 1995 and that eighteen patents met that criteria. (R 528A at 1). 215. Mitsubishi also maintained a chart tracking all ofRambus s issued US. patents. For example, one version of this chart begins with Rambus s first issued US. Patent No. 5 243 703 , at number one and concludes with US. Patent No. 5 578 940 which issued on November 26, 1996 at number twenty-seven. (R 2216 at 2 4). Rambus s ' 327 patent is listed at number twentythree on the chart. (R 2216 at 3). 216. A later version of the Mitsubishi chart contains thirty-seven Rambus patents and includes patents that issued in early 1998. (R 2218 at 3-6). 217. A Mitsubishi analysis of the claims of the PCT application specifically calls out the modifiable access time register and notes its similarity to SDRA latency control. (R 2213A 27). 218. An August 24, 1996 report on a Rambus meeting states: "Rambus' patents. Issued: , filed: 80. For example, data is transferred at both edges." (R 756A at 1). 219. As Complaint Counsel concede, Rambus has obtained patent claims that cover programmable CAS latency, variable burst length, dual-edge clocking, and on-chip DLL as those features are used in SDRAs and/or DDR SDRAs. (Complaint ,- 91). Rambus has asserted claims covering these four features against SDRAs and DDR SDRAs. (Complaint ,- 92). il. JEDEC IS A COLLABORATIV STANDARD SETTING BODY FOR THE SEMICONDUCTOR INDUSTRY Early History of JEDEC 220. JEDEC was founded in 1958 and originally named the "Joint Electron Device Engineering Council." (CX 302 at 10; I. Kelly, Tr. 1773-74 ("JEDEC has been active within an EIA organization under the name JEDEC since approximately 1958, and under other names with slightly different functions for a number of years prior to that, probably dating back to the 1940s. )). 221. The current name ofJEDEC is the "JEDEC Solid State Technology Association. (I. Kelly, Tr. 1750-51). 222. Between 1991 and 1996, JEDEC was an activity within the Electronic Industries Association ("EIA") Solid State Products Division, which was itself a division of the EIA' Components Group. (CX 3092 at 14 27; I. Kelly, Tr. 2075). 223. EIA is a "broad-based association that represents the electronics industry in the United States, and it engages in a variety of different activities in support ofthat industry. " (I. Kelly, Tr. 1750; CX 302 at 28). 224. In 1998, EIA changed its name to the Electronic Industries Alliance and JEDEC became a separate division ofEIA. (CX 302 at 11). In 1999, JEDEC became independently incorporated. (CX 302 at 11). 225. Both EIA and JEDEC are headquartered in Arlington, Virginia. (I. Kelly, Tr. 1751). The Purpose and Function of JEDEC 226. JEDEC seeks to create consensus based standards which refl