February 23 , 2004 Washington, D. C. ** PUBLIC VERSION ** TED STATES OF AMRICA FEDERA TRAE COMMSSION OFFICE OF ADMISTRATIVE LAW JUGES Docket No. 9302 In the Matter of RABUS INC. A CORPORATION INITIAL DECISION Before: Stephen 1. McGuire Chief Administrative Law Judge FEDERA TRAE COMMSSION APPEARCES FOR THE PARTIES Counsel Supporting the Complaint: M. Sean Royall Geoffey D. Oliver Patrick 1. Roach Of Counsel: Malcom L. Catt Robert P. Davis Michael A. Franchak Theodore A. Gebhard Andrew Heimert Charlotte Manning Lisa D. Rosenthal Sarah E. Schroeder Jerome A. Swindell John C. Weber Cary E. Zuk BURAU OF COMPETITION FEDERA TRAE COMMSSION Washington, D.C. 20580 Counsel for Respondent: Gregory P. Stone Steven M. Perry Peter A. Detre Sean P. Gates MUGER, TOLLES & OLSON LLP 355 South Grand Avenue, 35th Floor Los Angeles, California 90071- 1560 A. Douglas Melamed Kenneth A. Bamberger WIMER, CUTLER & PICKERIG LLP 2445 M Street, N. Washington, D. C. 20037 Sean C. Cunningham John M. Guaragna GARY, CARY, WAR & FREIDENRCHLLP 401 "B" Street, Suite 2000 San Diego, California 92101 II. TABLE OF CONTENTS PART ONE: INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FEDERA TRAE COMMSSION COMPLAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 II. RESPONDENT' S ANSWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 III. ISSUES PRESENTED . . . . . . . . . . . . . . . . . . . 3 IV. PROCEDUR BACKGROUN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 EVIDENCE. . . . . . . . . . . . . . . . . . . . . . . 5 VI. SUMARY OF THE DECISION . . . . . . . . . 6 PART TWO: FININGS OF FACT . . . . . . . . . 8 DRA AN THE INVENTIONS OF DRS. F AR ALD AN HOROWITZ . . . . . . 8 A. DRA Applications in Computer Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1. DRA Defined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. The Production of DRAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a. The DRA Manufacturing Process. . . . . . . . . . . . . . . . . . . . . . . 8 b. The Various Phases of DRA Development. . . . . . . . . . . . . . . . 9 c. Design Modification During DRA Production . . . . . . . . . . . . 10 The Memory Bottleneck Problem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Farmwald' s and Horowitz s Inventions Solve the Memory Bottleneck Problem by Addressing Numerous Issues . . . . . . . . . . . . . . . . . . . . 1. Electrical Issues . . . . . . . 14 2. Clocking Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. The Memory Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAUS: COMPAN DEVELOP.MENT AN PUBLIC PROMOTION OF TECHNOLOGY . . . . . . . . . . . A. The Founding of Ram bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1. Securing Venture Capital Funding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2. Early Business Plan for the FarmwaldlHorowitz Inventions. . . . . . . . . . 17 The RDRA Technology. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 The 1990 Business Plan . . . . . . . 20 RDRA Promotion and Licensing Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Presentation of the Rambus Inventions to the DRA Industry. . . . . . . . . . . . . 21 1. Rambus Visits to DRA Manufacturers and Systems Companies. . . . . 21 Preparation and Description of the Rambus Inventions Through Various Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 a. The May 1990 Techncal Description. . . . . . . . . . . . . . . . . . . . . 23 b. The November 1990 Technical Description. . . . . . . . . . . . . . . . 23 c. Siemens Responds With a List of Questions About Rambus Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 d. The April 1991 Techncal Description . . . . . . . . . . . . . . . . . . . . 25 The March 1992 Press Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Press Coverage: The March 1992 Microprocessor Report Aricle . . . . . . . . . . 27 Rambus s Disclosure ofInventions Through Public Documents . . . . . . . . . . . . 27 1. The 1992 Marketing Brochure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2. Publications Describing the First Rambus DRA . . . . . . . . . . . . . . . . . 28 Presentations of the Proprietary RDRA Technology and Nondisclosure Agreements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 The June 1992 Business Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Rambus Patent Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1. The ' 898 Patent Application . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . 30 2. The ' 703 Patent . . . . . . . . . . . 32 3. The PCT Application . . . 32 4. The ' 898 and PCT Applications Describe Numerous Inventions . . . . . . 32 a. Description of Access Time Registers . . . . . . . . . . . . . . . . . . . . 34 b. Description of Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 c. Description of Bus Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 d. Description of Variable Delay Circuitry With a Feedback Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Review of the ' 898 or PCT Application Should Have Raised Concerns That Rambus Might Be Able to Obtain Claims Over the Four Technologies at Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 JEDEC IS A COLLABORATIVE STANAR SETTING BODY FOR THE SEMICONDUCTOR INUSTRY ....................................... A. Early History of JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 B. The Purpose and Function ofJEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 C. The Organization ofJEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1. Member Companies . . . . 38 2. The JEDEC Council, Board of Directors and Offcers. . . . . . . . . . . . . . 39 3. The JC 42 Commttee. . . . . . 40 The Standard Development Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Rambus s Involvement in JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1. Rambus s Participation in JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Rambus Representatives Learn About the EINJEDEC Patent Policy . . 42 3. Rambus Continued to Stay Abreast of JEDEC and SyncLink Activities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 III. IV. EARY DEVELOPMENT AN ADOPTION OF JEDEC DRA STANARS. . . 44 A. The Initial SDRA Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1. Demand for a New Generation of Memory . . . . . . . . . . . . . . . . . . . . . . 44 2. Proposal of a Fully Synchronous DRA . . . . . . . . . . . . . . . . . . . . . . . . 45 3. Inclusion of Programmable CAS Latency and Burst Length . . . . . . . . . 47 4. Presentations of Additional Technologies . . . . . . . . . . . . . . . . . . . . . . . 50 a. Low Voltage Swing Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . 50 b. Dual Bank Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 c. Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 d. Source Synchronous Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . 51 e. Externally Supplied Reference Voltage ................... 52 5. Adoption of the SDRA Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6. Subsequent Proposals: Costs, CAS Latency and SDRA Lite. . . . . . . 53 B. . DDR SDRA - The Next Generation SDRA . . . . . . . . . . . . .. . . . . . . . . . . 54 1. Wark Within and Outside of JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2. Future Synchronous SDRA Features. . . . . . . . . . . . . . . . . . . . . . . . . 56 a. Presentation of Programmable CAS Latency and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b. Discussion ofPLL/DLL . . . . . . . . . . . c. Consideration of Dual Edge Clocking . . . . . . . . . . . . . . . . . . . . 59 Subsequent Proposed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 a. Externally Supplied Reference Voltage ................... 61 b. Source Synchronous Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . 61 Adoption of the DDR SDRA Standard . . . . . . . . . . . . . . . . . . . . . . . 61 Features Incorporated into the Standard. . . . . . . . . . . . . . . . . . . . . . . . . 62 a. On-Chip DLL ...................................... 62 b. Dual Edge Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c. Programmable CAS Latency and Burst Length . . . . . . . . . . . . . 62 Interoperability: The Effect of JEDEC' s Specifications versus Manufacturers Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RAIN AN SYNCLIN, THE SYNCLIN CONSORTIU, INTEL DRA MAACTURRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 A. The IEEE RamLink and SyncLink Working Groups. . . . . . . . . . . . . . . . . . . . . 63 1. The IEEE Membership Requirements and Lack of Patent Disclosure Obligations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 RamLink Was Developed to Standardize a New Future Memory Bus . . 63 The IEEE SyncLink Project Emanated From and Modified the Proposed RamLink Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Presentation of the RamLink/Synclink Architecture at JEDEC - Rambus Elects Not to Comment On Its Intellectual Property Position . . . . . . . . 64 Richard Crisp Indicates That the SyncLink Proposal May Infnge VI. Rambus Patents But Declines To Comment Regarding Rambus Intellectual Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Hyundai Negotiates "Other DRA Provision As Part ofIts RDRA License Agreement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 66 The SyncLink Consortium . . . . . . 67 1. Formation and Purpose of the Consortium . . . . . . . . . . . . . . . . . . . . . . 67 2. COJ;cern About Patents of Non-Members ....................... 68 3. SyncLink's Activities With Respect to Rambus Patent Applications and Intel' s Anounced Support ofRDRA ........................ Rambus s Relationships With Intel and DRA Manufacturers . . . . . . . . . . . . . 70 1. Rambus Sought Licenses and Support for RDRA From DRA Manufacturers Afer Intel Endorsed RDRA Technology . . . . . . . . . . 70 Intel and RDRA Royalty Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Design, Manufacture, and Supply of Memory Architectures by Micron and Other DRA Manufacturers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Cost Issues Associated With RDRA ......................... Actions by DRA Manufacturers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 The DRA Industry s Approach to Addressing RDRA Problems . . . 80 By 1998 the Rambus- Intel Relationship Was Deteriorating . . . . . . . . . . 81 Techncal Problems and Product Delays With RDRA . . . . . . . . . . . . . 81 Intel' s Announcement That It Would No Longer Support RDRA ... EINJEDEC PATENT POLICY ... .... ...... ....... . .. . ....... . .... .. . . . 83 A. Good Faith Obligations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 B. Open Standards . . . . . . . . . . . . . . . . . . . 85 C. Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1. JEP 21- ............................................... 86 2. JEP 21- . . . . . . . . . . . . . 86 3. EIA Legal Guides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4. EP- FandEP- A........................................ 91 5. ANSI Patent Policy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Committee Forms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 1. Membership Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' 93 2. Meeting Attendance Roster (Sign-In Sheet) ..................... 94 3. Committee Ballots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4. Members' Manual. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 96 5. Patent Tracking List . . . . . 97 Contemporaneous Correspondence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 1. The McGhee Memorandum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Correspondence Regarding the Dell Consent Agreement. . . . . . . . . . . . 98 3. Correspondence Regarding Micron Disclosure . . . . . . . . . . . . . . . . . . . 99 Conduct of Parties in JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 1. SEEQ Issue . . . . . . . . . . . . . . . 101 2. WANG Litigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3. ffM's Patent Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4. Hewlett Packard' s Patent Position ............................ 103 5. Texas Instruments' QUAD CAS Issue . . . . . . . . . . . . . . . . . . . . . . . . 103 6. Micron s Presentation on Burst EDO ......................... 104 7. Hyundai and Mitsubishi' s Presentation on SLDRA ............. 105 Trial Testimony . . . . . . . . . . . . . . . . . . . 105 1. A Policy in Transition. . . . . . . . . . . . . 105 2. Creation of Ambiguity and Confsion Regarding the Policy. . . . . . . . . 106 3. Unsuccessful Efforts to Expand the Patent Policy . . . . . . . . . .. . . . . . 107 4. Changes in Policy Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 a. EIA Patent Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 b. Changes Found in JEP 21-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Conflicts in the Trial Testimony 111 a. Trial Testimony Conficts Regarding Whether the Patent Policy Applied to Patent Applications and Intentions to File Patent Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Trial Testimony Conflicts Regarding Whether Members Should Disclose Actual Claims or Whether a Patent Number Was Suffcient. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Trial Testimony Conflicts Regarding Whether More Than Essential Patents Were Included in the Policy . . . . . . . . . . . . . 113 d. Trial Testimony Conflicts Regarding the Timing of Disclosure. . . . . . . 114 The Scope of the EINJEDEC Patent Policy. . . . . . . . . . . . . . . . . . . . . . . . . . 114 1. Disclosures Were Encouraged and Voluntary . . . . . . . . . . . . . . . . . . . 114 2. Patent Applications or Intentions To File Patent Applications Were Not Covered by the Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Members Were Encouraged To Disclose Patents That Were Essential To Practice the Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 There Was No Duty To Search for Intellectual Property Issues. . . . . . 116 The Policy was Limited To Participants With Actual Knowledge. . . . . 117 The Patent Policy Did Not Apply Afer a Company Withdrew From JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 If Disclosure Was Made, It Was Encouraged No Later Than the Time of Balloting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 VII. JEDEC 42.3 COMMTTEE MEMBERS WERE NOT MISLED BY RAUS ISSUES RELATING TO RAUS INTELLECTUAL PROPERTY. . . . . . . . . . . . 118 A. JEDEC Commttee Leaders and Members Were Fully Aware ofRambus Patents With Respect To Features Being Considered for Incorporation into JEDEC Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 1. Crisp Did Not Mislead JEDEC At the May 1992 Commttee Meeting VIII. RAUS WAS NOT IN VIOLATION OF ANY JEDEC RULES . . . . . . . . . . . . . . 134 A. Rambus Was Not in Violation of the JEDEC Patent Policy. . . . . . . . . . . . . . . 134 B. There Is No Evidence that Crisp, During the Time Rambus Participated in JEDEC, Had Actual Knowledge that Rambus Had Claims that Could Be Asserted Against JEDEC-Compliant SDRA or DDR SDRA Products . . . 134 Rambus Did Not Misappropriate Information From JEDEC . . . . . . . . . . . . . . 136 There Were No Prohibitions Which Precluded Rambus From Seeking Patent Protection For Inventions that Related to JEDEC Standards. . . . . . . . . . . . . . 136 Rambus Followed the Advice ofIts Legal Counsel in Determining Its Legal Obligations to JEDEC .......................................... 138 During the Time ofIts Participation in JEDEC Rambus Had No Intellectual Property Interests That It Would Have Been Required To Disclose Even If Disclosure Was Mandatory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 1. Rambus Had No Patents That It Was Required To Disclose . . . . . . . . 139 a. The ' 327 Patent Contains Various Limitations. . . . . . . . . . . . . 140 b. Rambus Had No Duty To Disclose the ' 327 Patent Based On the Hardell Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Rambus Had No Duty To Disclose the ' 327 Patent Based On the Survey Ballot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Rambus Had No Duty To Disclose the ' 327 Patent Based On the Samsung Presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Complaint Counsel Did Not Provide Suffcient Evidence Determne Whether the Presentations Would Trigger the Patent Policy. . . . . . . . . . . . . 141 Rambus Had No Undisclosed Patent Applications That It Was Required to Disclose, Even if the Policy Required Disclosure . . . . . . . 141 Regarding Rambus s Intent To Seek Patent Rights Over Certain SDRA Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 a. ffM and Siemens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 b. The May 1992 JC 42. 3 Meeting. . . . . . . . . . . . . . . . . . . . . . . . 120 c. PCT Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 d. Afer the May 1992 JC-42. 3 Meeting ................... 123 pcr Application Discussed At the September 1993 Meeting. . . . . . . . 124 The May 1995 JC 42. 3 Meeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 The September 1995 JC 42. 3 Meeting. . . . . . . . . . . . . . . . . . . . . . . . . 127 Rambus Met With Manufacturers and Suppliers . . . . . . . . . . . . . . . . . 128 JEDEC Members Viewed Rambus s Patents As a Collection of Prior Ar ................................................... 129 The Dell Consent Order and Rambus s Last JEDEC Meeting- December 1995 To January 1996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Ongoing Discussions of Rambus Patents by JEDEC Members Afer June 1996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1 THE EVIENCE DOES NOT SUPPORT COMPLAIT COUNSEL' ARGUMNT THAT THERE WERE VIABLE ALTERNATIVES TO RAUS' TECHNOLOGIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 A. The Testimony of Professor Jacob Regarding Allegedly Viable Alternatives Is Not Persuasive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Complaint Counsel Did Not Prove That There Were Viable Alternatives to the Rambus Technologies Adopted in the SDRA ....................... 167 1. Programmable CAS Latency. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 167 a. Complaint Counsel Did Not Prove That the Use of Fixed CAS Latency Parts Was a Viable Alternative. . . . . . . . . . . . . . . . . . 167 Complaint Counsel Did Not Prove That Programming CAS IX. XI. Rambus Withdrew From JEDEC Before Formal Work On the Standardization of the DDR SDRA Began. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Document Destruction by Rambus .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 RAUS HAS MONOPOLY POWER IN THE RELEVANT MARTS . . . : . . . 149 A. Relevant Markets. . . . . . . . . . . . . . . . . . . 149 1. Product Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2. Geographic Market. . . . 149 Monopoly Power . . . . . . . . . . . . . 150 1. Market Share . . . . . . . . 150 2. Assertion of Patents ...................................... 150 3. JEDEC Standardization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 a. Rambus s Market Power Is Not Attributable to the Inclusion of Its Technology In JEDEC Standards. . . . . . . . . . . . . . . . . . 152 Rational Manufacturers and a Rational Standard Setting Organization Would Have Stil Adopted the Rambus Technologies Had Disclosure Occurred. . . . . . . . . . . . . . . . . . 155 Intel' s Choice ofRDRA Conferred Market Power, Not JEDEC Standardization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 THE CHALENGED CONDUCT WAS NOT EXCLUSIONARY. . . . . . . . . . . . . . 157 A. Rambus Had a Legitimate Business Justification For Not Disclosing its Proprietary Patent Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Rambus s Conduct Did Not Impact Equal or Superior Alternatives . . . . . . . . 161 The "Commercial Viability" Analysis of Complaint Counsel' s Economic Expert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 The Assumption by Complaint Counsel' s Economic Expert that Rambus Knowingly Assumed the Risk Of Losing Its Ability To Enforce Its Patents. . . 163 The Assumption by Complaint Counsel' s Economic Expert That Rambus Violated a JEDEC Rule or Made Misrepresentations to JEDEC . . . . . . . . . . . 164 The Economic Evidence Regarding "Hold Up" and Disclosure Costs . . . . . . . 165 Vll Latency with Fuses Was a Viable Alternative. . . 171 Complaint Counsel Did Not Prove That Scaling CAS Latency With Clock Frequency Was a Viable Alternative . . . . . . . . . . . 173 Complaint Counsel Did Not Prove That Using Dedicated Pins to Identify the Latency Was a Viable Alternative. . . . . . . . . . . 174 Complaint Counsel Did Not Prove That Identifying CAS Latency in the Read Command Was a Viable Alternative. . . . . 176 Complaint Counsel Did Not Prove That Staying with Asynchronous Technology Was a Viable Alternative. . . . . . . . 177 Programmable Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 a. Complaint Counsel Did Not Prove That the Use of Pi xed Burst Length Parts Was a Viable Alternative . . . . . . . . . . . . . . . . . . 179 Complaint Counsel Did Not Prove That Programming Burst Length With Fuses Was a Viable Alternative. . . . . . . . . . . . . . 181 Complaint Counsel Did Not Prove That Using Dedicated Pins To Identify Burst Length Was a Viable Alternative . . . . . . . . . 182 Complaint Counsel Did Not Prove That Explicitly Identifying Burst Length in the Read Command Was a Viable Alternative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Complaint Counsel Did Not Prove That Using a Burst Terminate Command Was a Viable Alternative . . . . . . . . . . . . 183 Complaint Counsel Did Not Prove That Using CAS Pulse To Control Data Output Was a Viable Alternative 185 Given the Cost-Performance Differences, an Eco omically Rational DRA Manufacturer Would Have Adopted and Licensed the Rambus Technologies Incorporated In SDRA IfIt Had Known Of Ram bus Royalty Rates In Advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Complaint Counsel Did Not Prove That There Were Viable Alternatives To the Specified Rambus Technologies Adopted In DDR SDRA ........... 188 1. Dual-Edge Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 a. Complaint Counsel Did Not Prove That Interleaving On-Chip Banks Was a Viable Alternative. . . . . . . . . . . . . . . . . . . . . . . . 189 Complaint Counsel Did Not Prove That Interleaving On-Module Ranks Was a Viable Alternative. . . . . . . . . . . . . . . . . . . . . . . . 190 Complaint Counsel Did Not Prove That Increasing the Number of Pins on the DRA Was a Viable Alternative. . . . . . . . . . . . 192 Complaint Counsel Did Not Prove That Increasing the Number of Pins on the Module Was a Viable Alternative . . . . . . . . . . . 194 Complaint Counsel Did Not Prove That Doubling the Clock Frequency Was a Viable Alternative . . . . . . . . . . . . . . . . . . . . 194 Complaint Counsel Did Not Prove That Using Simultaneous Bi-directional I/O Drivers Was a Viable Alternative. . . . . . . . . 196 Complaint Counsel Did Not Prove That Using Toggle Mode Vll Was a Viable Alternative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 On-Chip DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 a. Complaint Counsel Did Not Prove That Putting a DLL On the Memory Controller Was a Viable Alternative. . . . . . . . . . . . . . 199 Complaint Counsel Did Not Prove That Putting a DLL On the Module Was a Viable Alternative . . . . . . . . . . . . . . . . . . . . . . 199 Complaint Counsel Did Not Prove That Using a Verner Method To Account For Skew Was a Viable Alternative. . . . . 201 Complaint Counsel Did Not Prove That Increasing the Number of Pins on the DRA Was a Viable Alternative. . . . . 202 Complaint Counsel Did Not Prove That Relying on the DQS Data Strobe Was a Viable Alternative . . . . . . . . . . . . . . . . . . . 202 Complaint Counsel Did Not Prove That Read Clocks Were a Viable Alternative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Given the Cost-Performance Differences, Economically Rational DRA Manufacturers Would Have Adopted and Licensed the Rambus Technologies Incorporated in DDR and SDRA ................ 203 EVEN ASSUMG THAT ALTERNATIVES DID EXIST, JEDEC WOULD NOT HAVE REJECTED THERAUS TECHNOLOGIES .... ........ . ......... 205 A. Whether JEDEC Would Have Adopted Alternatives To Rambus s SDRA and DDR Technologies Had Rambus Made Additional Disclosures. . . . . . . . . 205 JEDEC Might Not Have Sought a RA Assurance From Rambus Even if Rambus Had Made Disclosures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 If JEDEC Had Sought a RA Assurance, It Would Stil Have Adopted Rambus s Technologies . . . . . . . . . . . . 210 1. Rambus Would Have Given a RA Assurance. . . . . . . . . . . . . . . . . 210 2. It is Unlikely There Would Have Been Any Ex Ante Negotiations. . . . 213 3. JEDEC Would Have Adopted Rambus s Technologies with Rambus RA Assurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 XII. XIII. ANALYSIS OF THE BUT/FOR WORLD HYOTHESIS . . . . . . . . . . . . . . . . . . . . 218 A. The Revealed Preference Theory - JEDEC Continued To Select Rambus Technologies Even While Rambus Was Asserting Its Patent Rights . . . . . . . . 218 1. Proposed Alternatives Not Adopted By JEDEC ................. 219 a. Alternative To On-Chip PLL in DDR2 .................. 220 b. JEDEC Selection of Programmable CAS Latency . . . . . . . . . . 220 c. JEDEC Selection of Programmable Burst Length . . . . . . . . . . 221 d. JEDEC Selection of Dual-Edge Clocking . . . . . . . . . . . . . . . . 221 JEDEC Continued to View Rambus Patents As A Collection Of Prior ...................................................... 222 XIV. RAUS' S ROYALTY RATES AR IN FACT REASONABLE xv. NONDISCRIATORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 A. Rambus s Royalty Rates Are Reasonable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 1. The JEDEC Rules Defined "Reasonable" as the Rate Determned By the Market . . . . . . . . . . . 225 Rambus s Royalties Are Comparable To Other Licensing Rates in the Industry and Are "Reasonable" Under the JEDEC Rules. . . . . . . . . . . 226 Rambus s Royalty Rates Are Nondiscriminatory. . . . . . . . . . . . . . . . . . . . . . . 229 1. JEDEC Has Left the Definition of "Nondiscriminatory" to the Market and the Courts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 The Economic Evidence That Rambus s Royalty Rates Are Nondiscriminatory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 THE EVIENCE DOES NOT ESTABLISH THAT THE DRA INUSTRY IS LOCKED IN TO USING THE RAUS TECHNOLOGIES. . . . . . . . . . . . . . . . . . 231 A. An Historical Look at How the DRA Industry Transitions To New Technologies . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 1. Statistical Evidence of Co-Existing DRA Standards. . . . . . . . . . . . . 231 2. Industry Redesign of DRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 3. The Manufacture of Multiple DRAs to Accommodate New Technology. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 4. Coordination of New Industry Standards. . . . . . . .. . . . .. . . . . . . . . . 236 Switching Costs Do Not Support Theory ofIndustry Lock In. . . . . . . . . . . . . 238 1. Such Costs Are Not Prohibitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 2. Coordination Issues Would Not Preclude Switching to New Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 PART THRE: ANALYSIS AN CONCLUSIONS OF LAW . . . . . . . . . . . . . . . . . . . . . . 241 II. III. PROCEDUR ISSUES. . . . . . . . . . . . . . . . . . . 241 A. Standard of Proof. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 B. The Adverse Presumptions Are Not Material to the Disposition of the Case. . 243 1. The First and Second Adverse Presumptions Are Moot. . . . . . . . . . . . 244 2. The Five Remaining Adverse Presumptions Are Not Relevantto Any Material Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 3. A "Missing Witness" Inference Is Not Appropriate. . . . . . . . . . . . . . . 245 The Infineon Litigation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Jurisdiction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 OVERVIW OF VIOLATIONS ALLEGED ............................... 248 ELEMENTS OF LIABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 A. Possession of Monopoly Power in the Relevant Markets. . . . . . . . . . . . . . . . . 250 1. Relevant Markets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 a. Geographic Market. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 b. Product Markets . . . . . 251 2. Monopoly Power . . . . . 251 No Pattern of Anticompetitive Acts and Practices. . . . . . . . . . . . . . . . . . . . . . 253 1. The Legal Theory Upon Which Complaint Counsel Challenge Respondent's Conduct Lacks a Reasonable Basis in Law . . . . . . . . . . 254 Duties Upon Whch Complaint Counsel Base Their Challenge Must Be Clear. ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 The Evidence Presented at Trial Does Not Provide a Factual Basis for Finding a Pattern of Anticompetitive Acts and Practices . . . . . . . . . . . 260 a. No Duty to Disclose Intellectual Property Based on Good Faith . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 No Duty to Disclose Intellectual Property Based on Open Standards . . . . . . . . . 261 No Duty to Disclose Intellectual Property Based on the EINJEDEC Patent Policy. . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 i. Disclosure of Intellectual Property Under the EINJEDEC Patent Policy Was Voluntary . . . . . . . . . . 265 The EINJEDEC Patent Policy Was Limited to Issued Patents, Not to Patent Applications or Intentions to File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 The EINJEDEC Patent Policy Applied to Essential Patents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 The EINJEDEC Patent Policy Was Triggered At the Time of Submitting Committee Ballots. . . . . . . . . . . . . 271 The Unsuccessful Attempt to Expand the EINJEDEC Patent Policy Created Ambiguity and Confsion. . . . . . . . . . . . . . . . . 272 Rambus Had No Patents or Pending Patents That Would Have Been Required to be Disclosed by the EINJEDEC Patent Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 i. SDRA . . . . 274 ii. DDR-SDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 The Evidence Presented at Trial Does Not Provide a Factual Basis for Finding That Rambus Made Afrmative, Misleading Statements to JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Amendments to Claims to Broaden Patent Applications Were Not Improper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 No Exclusionary Conduct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 1. Exclusionary Conduct Defined . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . 286 2. Legitimate Business Justifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 3. Conduct Before Standard Setting Organizations . . . . . . . . . . . . . . . . . 289 4. Violations of Extrinsic Duties or Deception Afecting Consumers Not Exclusionary Conduct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 11. 111. IV. No Intent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 1. Intent Defined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 2. Complaint Counsel Have Not Demonstrated That Respondent Intended to Mislead or Deceive JEDEC ....................... 297 3. No Inference ofIntent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 4. Other Factors Demonstrating That The Intent Element Is Not Met . . . 299 No Causation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 1. Causation Defined. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 300 2. No Causal Link Between JEDEC Standardization and Respondent's Acquisition of Monopoly Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 a. Rambus Did Not Acquire Monopoly Power by Virtue of JEDEC's Standard Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Rambus Acquired Monopoly Power as a Result of its Superior Technology and Intel's Choice of its Technology. . . . . . . . . . . 303 3. No Reasonable Reliance by JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 4. No Inference of Causation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 No Anticompetitive Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 1. Anticompetitive Effects Defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 2. Complaint Counsel Have Not Demonstrated That There Were Viable Alternatives to Rambus Technologies . . . . . . . . . . . . . . . . . . . . . . . . . 312 a. Programmable CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . 313 b. Programmable Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . 314 c. Dual-edge Clocking. . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 d. On-Chip DLL ..................................... 315 Analysis of the Economic Evidence. . . . . . . . . . . . . . . . . . . . . . . . . . . 316 a. The Methodology Used by Complaint Counsel' s Economic Expert Is Flawed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 In the "But/For" World, JEDEC Would Not Have Rejected the Rambus Technologies Even if Alternatives Did Exist and Rambus Had Made the Additional Disclosures. . . . . . . . . . . . . 319 JEDEC's " Revealed Preference" For Rambus s Technologfes .. ...... ... ............... .... . . .......... . .. ... 322 Complaint Counsel Have Not Demonstrated That Rambus s Conduct Resulted in Higher Prices to Consumers . . . . . . . . . . . . . . . . . . . . . . . 323 a. Rambus s Royalty Rates Are Reasonable. . . . . . . . . . . . . . . . . 324 b. Rambus s Royalty RateS Are Nondiscriminatory . . . . . . . . . . . 325 JEDEC Is Not Locked In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 IV. SUMY OF LIABILITY ........................................... 329 PART FOUR: SUMY OF CONCLUSIONS OF LAW ......................... 329 ORDER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 XlI PART ONE: INTRODUCTION This Initial Decision is divided into four parts. Part One is the introduction, which includes a summary of the allegations contained in the Complaint; the defenses asserted in Respondent' s Answer; the issues presented; the procedural background; a comment on the evidence; and a summary of the decision. Part Two contains the separately numbered findings of fact. Part Three contains the analysis and conclusions oflaw, which provides an overview ofthe legal theories asserted by Complaint Counsel; sets forth the applicable law on each of the elements necessary to find a violation; and then applies the law to the facts established at trial. Part Four contains the summary of the conclusions oflaw and the Order of the Court. FEDERAL TRADE COMMISSION COMPLAINT The Federal Trade Commssion ("FTC") issued its Complaint in this matter on June 18 2002. The Complaint charges that Respondent, Rambus Inc. , a corporation, violated Section 5 of the Federal Trade Commssion Act ("FTC Act"), as amended. 15 U.S. c. 45. The Complaint charges Respondent with three violations. The first violation charges that Respondent engaged in a pattern of anti competitive and exclusionary acts and practices, whereby it obtained monopoly power in the synchronous DRA technology market and narrower markets encompassed therein, in violation of Section 5 of the FTC Act. (Complaint,- 122). The second violation charges that Respondent engaged in a pattern of anticompetitive and exclusionary acts and practices with a specific intent to monopolize the synchronous DRA technology market and narrower markets encompassed therein, resulting, at a minimum, in a dangerous probability of monopolization in each ofthe markets, in violation of Section 5 of the FTC Act. (Complaint ,- 123). The third violation charges that Respondent engaged in a pattern of anti competitive and exclusionary acts and practices, whereby it unreasonably restrained trade in the synchronous DRA technology market and narrower markets encompassed therein, which acts and practices constitute unfair methods of competition in violation of Section 5 of the FTC Act. (Complaint ,- 124). The Complaint alleges that Respondent participated in the work of the JEDEC Solid State Technology Association ("JEDEC"), an industry standard setting organization in which Respondent was a regular participant, without making it known to JEDEC or to its members that Respondent sought to obtain patents on technologies adopted in the relevant JEDEC standards. (Complaint,-,- 2 , 44, 45 , 46). Respondent's alleged scheme further entailed perfecting its patent rights over these same technologies and then, once the standards had become widely adopted within the DRA industry, enforcing such patents worldwide against companies manufacturing memory products in compliance with the JEDEC standards. (Complaint,-,- 2 , 45 , 46). Respondent is alleged to have concealed information in violation ofJEDEC' s operating rules and procedures which Complaint Counsel argue imposed upon JEDEC members an obligation to "disclose any patents, or pending patent applications, involving the standard-setting work." (Complaint,-,- 20, 21 , 24, 79). In addition, the Complaint alleges a "basic rule" of JEDEC to avoid a,nticompetitive activity and a commtment to avoid, where possible incorporation of patented technologies. (Complaint,-,- 17 22). The Complaint alleges that Respondent violated these duties by conveying to JEDEC the materially false and misleading impression that it possessed no relevant intellectual property rights. (Complaint,-,- 2 , . 80). The Complaint further alleges that Respondent s conduct caused anticompetitive effects including increased royalties, increase in the price of synchronous DRA and products incorporating synchronous DRA, decreased incentives to produce memory using synchronous DRA technology, and harms to standard setting organizations and activities. (Complaint ,-,- 119, 120). ll. RESPONDENT' S ANSWER In its Answer filed on July 29, 2002, Respondent alleged as an affrmative defense that the Complaint failed to state a claim under Section 5 of the FTC Act. The Answer denied the material allegations of the Complaint and asserted that the evidence would show that JEDEC' rules and policies did not impose, and were not commonly understood to impose, the disclosure obligations set out in the Complaint. (Answer, pp. 1-2). Respondent asserted in its Answer that the evidence would show that it did not have, until after it left JEDEC, any undisclosed patents or patent applications that contained claims reading on devices manufactured in accordance with any JEDEC standard. (Answer, p. 2). Respondent also asserted in its Answer that the evidence would show that JEDEC did not rely on any purported silence on Respondent's part at JEDEC meetings and instead chose to adopt certain technologies because ofthe cost/performance advantages of those technologies and the absence of reasonable alternatives. (Answer, p. 2). Respondent's Answer asserted that in light of the absence of a duty to disclose , in light of the absence of pending claims reading on JEDEC standards, and in light of the other evidence to be considered at trial, it would be clear that Respondent' s alleged failure to disclose its potential intellectual property claims had no anticompetitive effect in any market and that Respondent had not violated Section 5. (Answer, pp. 1-3). il. ISSUES PRESENTED The issues presented in this case are: (1) whether Respondent engaged in a pattern of deceptive, exclusionary conduct by subverting an open standards process; (2) whether Respondent utilized such conduct to capture a monopoly in technology-related markets; (3) whether Respondent' s challenged conduct violated principles of antitrust law; and (4) whether Respondent' s conduct resulted in anti competitive injury. IV. PROCEDURAL BACKGROUND On June 18, 2002, the Commssion issued its Complaint. This case was initially assigned to Administrative Law Judge ("ALr') James P. Timony. Rambus filed a motion to stay the proceeding until the Federal Circuit issued its decision in Rambus Inc. v. Infineon Technologies an appeal of a jury verdict against Rambus. The Federal Circuit reversed the jury verdict of fraud and remanded the case, as discussed more fully in Part III, Section I. C. An Order Denying Motion for Stay was issued in this case on July 18 2002. On July 29 2002, Rambus filed its Answer in this matter. On February 26 2003 , ALJ Timony issued an Order On Complaint Counsel' s Motions For Default Judgment and For Oral Argument which imposed seven rebuttable presumptions against Rambus based on a finding of intentional destruction of evidence. This Order is discussed in Part III, Section I.B. On February 28 2003 , ALJ Timony retired from federal service. Stephen 1. McGuire was subsequently appointed FTC Chief Administrative Law Judge and assigned the Rambus matter. Trial in this proceeding commenced on April 30, 2003. The 54 day administrative hearing produced a voluminous evidentiary record including 44 live witnesses, 1 770 admitted exhbits nearly 12 000 pages of trial transcript, and hundreds of pages of deposition transcripts. The last day on which testimony was received was August 1 , 2003. The paries then filed Post-Trial Briefs, Proposed Findings of Fact, and Conclusions of Law, and replies thereto. Closing arguments and oral examination by the Court was conducted on October 8 2003. Following the closing arguments, the hearing record was closed pursuant to Commssion Rule 3.44(c), by Order dated October 9, 2003. Due to the exceptional circumstances of the complexity of the issues presented, the volumes of evidence introduced at trial, and review of the comprehensive proposed findings offact and post-hearing briefs, it was necessary to extend the deadline for filing the Initial Decision within one year of the issuance of the Complaint. By Order dated December 23 , 2003 the Commssion also extended the time for filing the Initial Decision within 90 days of the close of the hearing record until February 17, 2004. EVIENCE The Initial Decision is based on the transcript of the testimony, the exhbits properly admitted in evidence, and the proposed findings of fact, briefs, conclusions of law, and replies thereto filed by the parties. Once a finding of fact is established, it is cited to in subsequent sections or in the analysis by the designation " The parties submitted extensive post-trial briefs and reply briefs. The Initial Decision addresses only material issues of fact and law. Proposed findings offact not included in the This opinion uses the following abbreviations for citations: Compo - Complaint F. - Finding of fact CX - Complaint Counsel Exhbit RX - Respondent Exhbit JX - Joint Exhbit Tr. - Transcript of Testimony before the Administrative Law Judge Dep. - Transcript of Deposition Stip. - Stipulation CCPFF - Complaint Counsel' s Proposed Findings of Fact CCPHB - Complaint Counsel' s Post-Hearing Brief CCPHR - Complaint Counsel' s Post-Hearing Reply Brief RPHB - Respondent's Post- Hearing Brief RPHR - Respondent's Post-Hearing Reply Brief Initial Decision were rejected, either because they were not supported by the evidence or because they were not dispositive to the determination of the allegations contained in the Complaint. The Commssion has held that Administrative Law Judges are not required to discuss the testimony of each witness or all exhbits that are presented during the administrative adjudication. In re Amrep Corp. 102 F.T.c. 1362, 1670 (1983). Further, administrative adjudicators are "not required to make subordinate findings on every collateral contention advanced, but only upon those issues of fact, law, or discretion which are ' material.'" Minneapolis St. Louis Ry. Co. v. United States 361 U.S. 173 , 193-94 (1959). Many of the documents and parts of the oral testimony were received into the record camera. Where an entire document or where certain trial testimony was given in camera treatment for trial, but the portion of the document or the trial testimony utilized in this Initial Decision does not rise to the level necessary for in camera treatment, such information is disclosed in the public version of this Initial Decision, pursuant to Commssion Rule 3.45(a) (the ALJ "may disclose such in camera material to the extent necessary for the proper disposition of the proceeding ). In accordance with 16 c.F.R. ~ 3.45(f), material that has been given in camera treatment is indicated in bold font and braces in the in camera version. Where in camera material had been redacted from the public version of the Initial Decision, braces precede the redacted material. VI. SUMMARY OF THE DECISION Complaint Counsel have failed to sustain their burden of proof with respect all three of the violations alleged in the Complaint. First, the evidence at trial establishes that Complaint Counsel failed to prove the facts they alleged in the Complaint. Second, an analysis of the legal theories advanced by Complaint Counsel demonstrates that there is no legal basis for finding a violation of Section 5 of the Federal Trade Commssion Act, either as based on other antitrust laws or solely as an unfair method of competition. Third, an application of the facts established at trial to the legal theories asserted leads to the conclusion that Complaint Counsel have failed to prove their case. The evidentiary record demonstrates that: (1) the EINJEDEC patent policy encouraged the early, voluntary disclosure of essential patents and Respondent did not violate this policy; (2) the case law upon which Complaint Counsel rely to impose antitrust liability is clearly distinguishable on the facts of this case; (3) Respondent s conduct did not amount to deception and did not violate any "extrinsic duties " such as a duty of good faith to disclose relevant patent information; (4) Respondent did not have any undisclosed patents or patent applications during the time that it was a JEDEC member that it was obligated to disclose; (5) amendments to broaden Respondent's patent applications while a member of JEDEC were not improper , either as a matter of law or fact; (6) by having a legitimate business justification for its actions, Respondent did not engage in exclusionary conduct; (7) Respondent did not intentionally mislead JEDEC by knowingly violating a JEDEC disclosure rule; (8) there is no causal link between JEDEC standardization and Respondent's acquisition of monopoly power; (9) members of JEDEC did not rely on any alleged omission or misrepresentation by Respondent and, if they had, such reliance would not have been reasonable; (10) the challenged conduct did not result in anticompetitive effects, as Complaint Counsel did not demonstrate that there were viable alternatives to Respondent's superior technologies; (11) the challenged conduct did not result in anti competitive effects as the challenged conduct did not result in higher prices to consumers; and (12) JEDEC is not locked in to using Respondent's technologies in its current standardization efforts. For these reasons, Complaint Counsel have failed to sustain their burden to establish liability for the violations alleged. Accordingly, the Complaint is DISMISSED. PART TWO: FINDINGS OF FACT DRAM AND THE INVENTIONS OF DRS. FARMALD AND HOROWITZ DRAM Applications in Computer Systems DRAM Defined 1. DRA stands for "dynamic random access memory." (Rhoden, Tr. 266). DRA is a type of electronic memory. (Roden, Tr. 266). DRA is "dynamic" because it needs to be refreshed every fraction of a second. (Rhoden, Tr. 266-67). 2. The primary use for DRA is in computer systems. (Roden, Tr. 267-68; Gross, Tr. 2272-73). 3. DRAs are also used in a wide range of other products involving computer systems. (Sussman, Tr. 1362). These products include printers, PDAs (personal digital assistants), and cameras. (Kellogg, Tr. 4986-87; Tabrizi, Tr. 9126-27; Krashinsky, Tr. 2770-71; Farmwald, Tr. 8206-07; Gross, Tr. 2272-73). 4. Typically, multiple DRA chips are placed on a memory module, which is a small printed circuit board. (Roden, Tr. 272-73). The module containing the DRA chips connects to a motherboard. (Rhoden, Tr. 270 273). In some applications, such as graphics cards, the DRA chips are not put in memory modules. (Wagner, Tr. 3871-72). 5. A DRA is made up of a number of cells. (Rhoden, Tr. 359). Information is stored in the cell capacitor as either a high or low voltage. (Roden, Tr. 359). The cells of the DRA are divided into an array via a series of rows and columns with the cells located at the intersections of those rows and columns. (Roden, Tr. 359-60). Access to the cell capacitor is made by activating a transistor, which transfers the voltage in the capacitor to a column, also known as a bit line. (Roden, Tr. 359-60). 6. In order for a DRA to have any value, it must be compatible and interoperable with the other components in the same specific system that include the DRA. (Peisl, Tr. 4410; CX 1075 at 1; Heye, Tr. 3655-65; Jacob, Tr. 5562-66). The Production of DRAMs The DRAM Manufacturing Process 7. The starting point in the manufacturing process is a bare silicon wafer. (Becker, Tr. 1116- 17). 8. During the course of the manufacturing process, successive layers are built up on the silicon wafer. (See generally Becker, Tr. 1116-32). DRAs require as many as twenty-two . distinct layers. (Becker, Tr. 1131). Each layer requires a series of manufacturing steps. (Becker Tr. 1131-32). Processing the wafer takes about four hundred manufacturing steps. (Becker, Tr. 1118, 1131). 9. The manufacturing process is nonlinear, meaning that a wafer wil reenter different processing areas of the fab a number oftimes. (Becker, Tr. 1118). A processed wafer contains hundreds of individual DRA chips. (Becker, Tr. 1117). 10. The processed wafer is electrically tested in order to find the good chips. (Becker Tr. 1132-34). Such testing, however, does not identify all of the die with disqualifying defects. More stringent testing is only possible after the die have been packaged. (Geilhufe, Tr. 9570). 11. Afer testing, the wafer is cut into individual DRAs. (Becker, Tr. 1132-34). The individual chips are then bonded to a metal lattice like structure called a lead frame and are covered with a black hard plastic mold compound. (Becker, Tr. 1132-34). 12. Afer packaging, the good chips are built into components and tested again. (Becker Tr. 1135-36). 13. The tested components may also be assembled onto circuit boards to create modules and are further tested. (Becker, Tr. 1135; see generally Becker, Tr. 1132-36 (describing the process of how the chips are built into components and connected to modules)). 14. The largest part of a DRA, approximately ninety percent of the active area, consists of the memory array, that is the memory cells and related circuitry. (Geilhufe, Tr. 9560). The remaining ten percent consists of peripheral circuitry. (Geilhufe, Tr. 9560). Circuitry for implementing the four features at issue here - programmable column address strobe ("CAS" latency, programmable burst length, dual edge clocking, and on-chip delay lock loop ("DLL" ) - are found in the peripheral circuitry. (Geilhufe, Tr. 9559). 15. The vast majority of DRA development costs is spent on the memory arrayportion of the DRA, including the manufacturing process and equipment development. (Geilhufe, Tr. 9560-61). Development costs for the peripheral circuitry are much lower. (Geilhufe, Tr. 9560- 61). The Various Phases of DRAM Development 16. The development ofthe DRA proceeds along a number of "phases" and milestones. Those are the design phase, the layout phase, the simulation phase, the verification phase, tape out, initial silicon, the validation phase, internal qualification phase, and the production phase. (Shirley, Tr. 4141-42; Reczek, Tr. 4306-41). 17. In the design phase, the DRA designers implement the DRA specification as a set of circuit designs or schematics. (Shirley, Tr. 4142-43). 18. In the layout phase, the layout designers take the circuit designs created in the first step and create a representation of the circuit designs. (Shirley, Tr. 4143). 19. In the simulation phase, the design engineers simulate the designs in order to verify that the chips wil perform as intended before they are first manufactured. (Shirley, Tr. 4144). 20. The verification phase involves ensuring that the schematics created in the design phase are in fact represented by the work done in the layout phase. (Shirley, Tr. 4144-45; Reczek, Tr. 4309). 21. Tape out involves the process of transferring the DRA layout onto masks that wil be used in the fabrication ofthe DRA. (Shirley, Tr. 4145). The collection of individual masks necessary to fabricate a DRA design comprises a mask set. (Shirley, Tr. 4147). 22. A mask contains an image that is transferred to the wafer through a process of using light to expose the wafer to the image pattern in the mask and using gasses to etch the resulting pattern into the wafer. (Becker, Tr. 1122-24). 23. At some DRA manufacturers, including Micron Technologies, Inc. ("Micron ), the physical creation of masks is done by specialized firms that provide the service to the DRA manufacturers. (Shirley, Tr. 4145-46). Other DRA manufacturers, including Infneon Technologies ("Infneon ), produce their own masks. (Reczek, Tr. 4312). 24. The mask set, once it is received, is used to create the first physical manfestation the DRA chips on wafers. Those wafers represent a milestone and are referred to as "initial silicon. " (Shirley, Tr. 4147). 25. Initial silicon is then tested in the validation and internal qualification phases to ensure that the DRA on the wafers operate the way they were intended (the validation phase) and that the DRA on the wafers operate appropriately in the expected environments (the qualification phase). (Shirley, Tr. 4148-49). Design Modifcation During DRAM Production 26. The DRA industry transitions between different versions of DRA quite frequently. As a witness from Micron explained: Switching from one product to another, while stil using the same core technology, involves only changing priorities in design and product engineering and may mean some differences in our assembly and test equipment purchases. SDRA, SLDRA, nDRA all use the same fab equipment and core DRA technology. In short, while the flavors might change, it' s stil a DRA. (R 836 at 3) (emphasis added). The Memory Botteneck Problem 27. Dr. Michael Farmwald, one of the two founders of Ram bus, received his bachelor degree in mathematics from Purdue University in 1974. (Farmwald, Tr. 8058). He then earned a Ph.D. in computer science from Stanford University in 1981. (Farmwald, Tr. 8059). Whle a graduate student at Stanford, Dr. Farmwald was in charge of a supercomputer project at Lawrence Livermore National Labs. (Farmwald, Tr. 8059). Afer obtaining his Ph. , he continued to work at Livermore for four years and then founded a company called FTL (which stood for "Faster Than Light"), whose goal was to build very fast computers. (Farmwald Tr. 8060-61). In 1988, Dr. Farmwald went to the University ofIllnois to teach in the computer science department. (Farwald, Tr. 8063-64). 28. While working as a professor at the University of Ilinois, Dr. Farmwald realized, and it was a general perception in the DRA industry, that developments in microprocessor technology would lead to significant speed increases in microprocessors while memory chip performance would not keep up. (Farmwald, Tr. 8063 , 8067). He recognized that the result of these trends would be a "bottleneck" - memory technology would limit computer system performance. (Farmwald, Tr. 8068-69). 29. Moore s law, named after Gordon Moore, founder ofIntel Corp. ("Intel"), predicts that processor speeds wil increase by a factor offour every three years. (Farmwald, Tr. 8068). This "law" has held true for over the last two decades. (Farmwald, Tr. 8068). The performance of DRAs, however, was increasing at a lesser rate; while DRAs were fast in comparison to microprocessors in the early 1980s, as an historical matter, DRA performance had increased very slowly over time. (Farmwald, Tr. 8072). 30. Graphing predicted microprocessor speeds against memory performance Dr. Farmwald predicted an ever increasing gap between microprocessor performance and DRA performance. (Farmwald, Tr. 8071-73). 31. Assuming that the predicted DRA speeds were not improved, Dr. Farmwald projected that the number of DRAs needed to support future microprocessors would become extremely large over time. (Farmwald, Tr. 8073). 32. The increasing number of DRAs needed to support faster computers was also consistent with Dr. Farmwald' s experience that microprocessors were demanding higher and higher bandwidth memory systems ("bandwidth" being the amount of information that can be transferred over a specific period oftime). (Farmwald, Tr. 8076-79). 33. Dr. Farmwald also plotted the projected price for computers, which showed that the cost for computer systems was dropping over time. (Farmwald, Tr. 8074-75). Comparing these projected costs with the number of DRAs that would be required to support the bandwidth needs offaster microprocessors, Dr. Farmwald knew that "there was something broken" - the costs of the thousands of DRAs needed at higher microprocessor speeds would prevent the decline of computer system prices. (Farmwald, Tr. 8075-76). 34. Later, a 1992 Rambus "Corporate Backgrounder" described the issue: " (o)ne of the most serious problems is the chronic speed mismatch between processors and main memory. Designers refer to this as the memory bottleneck. The data transfer rates of memory ICs (integrated circuits) lag far behind a processor s ability to handle the data." (R 81 at 4). 35. To meet the higher bandwidth needs of microprocessors without the overwhelming cost of thousands of DRAs, DRA performance had to increase at a higher rate. (Farmwald Tr. 8076). 36. Years later, Dr. Farmwald' s 1988 observations were recognized by others in the industry. For example, an April 1992 internal memorandum of Siemens AG ("Seimens ) states that " (a)s a result of the trend toward increasingly faster RISC and CISC processors, the DRA interface has become more and more of a problem for system developers. In order to eliminate this data transmission rate bottleneck, various competing concepts regarding the design of newer DRAs have emerged. . . ." (RX 285A at 1). 37. Similarly, an October 1992 article published in the Institute of Electrical and Electronic Engineers, Inc. ("IEEE") Spectrum warned , " (i)fthe price-to-performance ratio of computer systems is to keep improving, the gap in speed between processors and memory must be closed." (RX 329 at 1). IEEE Spectrum is the overall general magazine for the IEEE, a professional organization of electronic and electrical engineers. (prince, Tr. 8972-73). The article went on to explain that "the accepted dynamic RA (DRA) architectures and solutions have been pushed to their limits. A basic change in architecture seems the only way to obtain an urgently needed increase in memory speed." (RX 329 at 1). This article reflected a general discussion within the industry in 1992 that computer companies needed faster DRAs. (prince Tr. 8977-78). 38. Another article in the October 1992 IEEE Spectrum stated , " (i)f dynamic RAs and processors are to trade data at close to top speed, the interface between them must be reengineered. . . . None of the types of interfaces now popular can do this while conserving power and cost to the desired degree." (R 333 at 1). 39. In February 1994, Dr. Betty Prince, a long-time consultant in the DRA industry and the author of five books on DRA technologies (prince, Tr. 8970-72), wrote in an article published in IEEE Spectrum that " (t)he mismatched bandwidths of fast processors and the slower memory chips they must employ are a problem of long standing. Processors now as always require more data per unit time than many standard memory chips have been designed to provide. " (RX 465 at 1). She also provided a graph showing that this performance gap was increasing over time. (RX 465 at 1). Dr. Prince agreed that the performance gap she wrote about created a bottleneck. (prince, Tr. 8990-91). 40. Intel saw the memory bottleneck coming in 1995 , and the recognition of this bottleneck prompted Intel to investigate various memory technologies in an effort to remedy the situation. (MacWillams, Tr. 4929-30). Farmwald' s and Horowitz s Inventions Solve the Memory Bottleneck Problem by Addressing Numerous Issues 41. In 1988, Dr. Farmwald conceived the general idea of a new memory interface and protocol (an organization of the bits and timing of bits transferred by a memory chip) that would allow a single DRA chip to have higher performance than a board Dr. Farmwald had designed containing 320 existing DRA chips. (Farmwald, Tr. 8086-88). 42. In order to progress beyond his initial ideas Dr. Farmwald realized that he needed the assistance of an expert in circuit design. (Farmwald, Tr. 8089). Dr. Farmwald sought the help of a former colleague - Dr. Mark Horowitz, a professor at Stanford. (Farmwald, Tr. 8089-90). 43. Dr. Horowitz had completed both his bachelors and masters degrees in electrical engineering from MIT in four years, receiving the degrees in 1978. (Horowitz, Tr. 8477). Afer working for a year at Signetics, he then earned a Ph.D. in integrated circuit design from Stanford University in 1983. (Horowitz, Tr. 8477-80). Dr. Horowitz has been a professor in the electrical engineering and computer science departments at Stanford University since the mid- 1980' (Horowitz, Tr. 8476). Dr. Horowitz currently holds two endowed chairs at Stanford. (Horowitz Tr. 8482). 44. Dr. Farmwald convinced Dr. Horowitz to take a year s leave from Stanford to further explore their ideas. (Farmwald, Tr. 8092-93). Starting in the spring of 1989, the two worked from Dr. Horowitz s Palo Alto home. (Farmwald, Tr. 8093-94). 45. Dr. Horowitz s goal was to build the fastest possible DRA interface. (Horowitz Tr. 8486). Drs. Horowitz and Farmwald determined that 500 megahertz ("MH") DRA operation might be possible, and they worked toward that goal. (Horowitz, Tr. 8505-06). 46. In creating their inventions, Drs. Farmwald and Horowitz had to solve numerous problems. (Horowitz, Tr. 8487). They realized that current memory interfaces could not run at high speeds as a result of electrical issues, clocking issues, and issues relating to the protocol, and that they would need innovations in each of these areas in order to meet their goal. (Horowitz Tr. 8487-88). Electrical Issues 47. With respect to electrical issues, Drs. Farmwald and Horowitz needed to develop driver and receiver circuitry that could generate very high-speed signals, and they also needed to develop a bus that would allow the signals to propagate. (Farmwald, Tr. 8118-20; Horowitz Tr. 8488). 48. Drs. Farmwald and Horowitz developed a number of solutions to the electrical issues that arose. First, they realized that reflected signals from the end of the bus lines would be a serious problem at high speeds and conceived the idea of introducing resistors to "terminate" the bus lines and reduce reflections. (Horowitz, Tr. 8492-93). 49. Second, Drs. Farmwald and Horowitz realized that the high voltage signaling then in use would generate too much power at high speeds, and they developed low voltage signaling using a particular kind of driver called a "current mode" or "current source" driver. (Farmwald Tr. 8119, 8144-45; Horowitz, Tr. 8494-95; RX 82 at 9). 50. Third, Drs. Farmwald and Horowitz realized that they could not build a 500 DRA with current technology and so, to transmit data at the highest possible speed, they conceived the idea of transmitting and receiving data on both edges of a 250 MH clock. (Farmwald, Tr. 8118; Horowitz, Tr. 8495-97). Clocking Issues 51. With respect to clocking issues, Drs. Farmwald and Horowitz realized from personal experience that, although current memory chips were asynchronous, they would have to develop a synchronous device with mechanisms for exercising very tight control over timing with respect the clock to make sure that each bit of data - traveling at a very high speed - was sampled at the right time. (Horowitz, Tr. 8488-89; see infra F. 52- , 284 for discussion of asynchronous versus synchronous devices). 52. Drs. Farmwald and Horowitz decided to design a synchronous system since the timing reference provided by a clock could be used to limit timing uncertainties in the system and allow for high speed performance. (Horowitz, Tr. 8499-502). 53. Even in a synchronous system there remain some timing uncertainties; for example expected delays of the buffers may vary from DRA to DRA due to differences in their fabrication. (Horowitz, Tr. 8503-04). In order to have the highest speed possible, Drs. Farmwald and Horowitz wanted to minimize this remaining uncertainty to the extent possible; they therefore came up with the idea of using a delay locked loop (DLL) or a phase locked loop (PLL) on-chip. (Farmwald, Tr. 8118; Horowitz, Tr. 8504). The Memory Interface Protocol 54. With respect to the design of the protocol, additional optimizations developed for high speed operation included returning a variable amount of data in response to a request rather than a single bit of data and by putting registers and associated control circuitry directly on the DRA. (Farmwald, Tr. 8115; Horowitz, Tr. 8489-90). 55. With respect to the protocol, Drs. Farmwald and Horowitz again came up with various innovations. As one example, they decided to put registers on the DRA to make the interface more effcient. (Farmwald, Tr. 8115- 16; Horowitz, Tr. 8506). These registers would be programmed with parameters, such as the address range that a particular DRA would respond to or the access time of the DRA. (Horowitz, Tr. 8507, 8509- 10). 56. Drs. Farmwald and Horowitz wanted to make the access time variable for two reasons. First, if the bus were improved so that it could operate at a faster clock frequency, the access time ofthe DRA could be adjusted so that it would operate with that faster clock. Second, a variable access time would allow the access times of all the DRAs in a system to be adjusted to have the same access time. (Horowitz, Tr. 8510- 11). 57. As another example of an innovation related to the protocol, Drs. Farmwald and Horowitz allowed the response to a request to include a variable amount of data, a feature known as "variable block size" or "variable burst length." (Farmwald, Tr. 8116- , 8146; Horowitz Tr. 8512; RX 82 at 9). ll. RAMBUS: COMPANY DEVELOPMENT AND PUBLIC PROMOTION OF TECHNOLOGY The Founding of Rambus 58. Drs. Farmwald and Horowitz founded "Rambus Inc. " in March of 1990. (CX 545 at 5; RX 81 at 19). By 1992, its headquarters were located in Mountain View, California, in Silicon Valley. (RX 81 at 1, 3). 59. Rambus is, and at all relevant times has been, a corporation as "corporation" is defined by Section 4 ofthe Federal Trade Commssion Act, 15 US. C. ~ 44; and at all relevant times has been and is now engaged in commerce as "commerce" is defined in that same provision. (Answer, ,-,- 5 , 6). 60. Rambus designs, develops, licenses, and markets both nationally and internationally, high-speed chip connection technology to enhance the performance of computers, consumer electronics, and communications systems. (Answer ,- 5). Rambus is a pure-play licensing company; it does not manufacture DRA, but rather uses research and development to invent new DRA technologies and makes its money by licensing its technology to others. (Teece, Tr. 10350-51). 61. For the fiscal year that ended on September 30 2001 , Rambus reported revenues of approximately $117 millon. (Comp. ,- 5; Answer ,- 5). 62. Rambus s founders intended to improve memory performance through multiple inventions based on modifications of standard DRAs (see CX 533 at 2), which could be used separately or in combination(s). The greatest performance gains would be realized by using these inventions in combination. Rambus DRA or "RDRA is the name for the "revolutionary DRA architecture and high speed chip-to-chip data transfer technology" that incorporates several ofRambus s inventions, including its proprietary bus technology. (RX 81 at 3). Each of the various generations ofRDRA are manufactured in accordance with specifications established through a collaboration among Rambus and its DRA partners. (Farmwald Tr. 8149, 8241). 63. Early on, Rambus realized that it was important to its business strategy to protect the intellectual property rights to its technology. (CX 535 at 1). Part of its early strategy to do this was to pursue an application for "a basic, broad patent filed in all major industrial nations" and thereafter "follow up with additional patents on inventions created during the development of the technology. " (CX 535 at 1). It was also important to Rambus to enter into nondisclosure agreements with companies exposed to its technology. (CX 535 at 1). 64. The only business model that "made any sense" to Rambus co-founder Michael Farmwald "was to patent (the technology), convince others to build it, and charge them royalties because "( w )hen we were first formed, it was my view that we could not possibly raise enough money to build DRAs. DRA fabs cost, even back then they cost, (sic) order of a bilion dollars. You couldn t really build DRAs without owning your own fab, and so a business plan which involved actually building and sellng DRAs was hopeless, and so from the very beginnng we were a royalty-based company. " (Farmwald, Tr. 8095; CX 2106 at 27 (Farmwald Dep. )). 65. Rambus s primary objective was to commercialize the revolutionary inventions Drs. Farmwald and Horowitz had created in the form of an open industry de facto standard, and to ensure that the standard "didn t go off in incompatible directions." (Farmwald, Tr. 8110, 8125- , 8148). 66. Rambus contemplated that it would earn its income by working with DRA companies to implement the Rambus interface in their products, and, for that work, get paid consulting fees (for the time its engineers spent working with partners) and royalties for the use of Rambus s intellectual property that would be incorporated into DRA companies' products. (Farmwald, Tr. 8150). 67. To become and remain a viable company, it intended to charge low single digit royalties, which it believed to be fair in light of the importance ofRambus s intellectual property contribution to the product and the large size of the DRA market. (Farmwald, Tr. 8128; Cf( 1282 at 5). 68. Rambus founder Farmwald knew that companies never like to pay royalties unless they have to and they can not "get out of it." (CX 2106 at 27 (Farmwald, Dep. )). Securing Venture Capital Funding 69. In an effort to receive funding for the start-up of Ram bus Inc. , the founders approached various venture capital firms: Kleiner Perkins, one of the largest venture capital firms in the world; Merrill Pickard Anderson and Eyre; and Mohr Davidow. (Farmwald, Tr. 8099). As part of the meetings with the venture capital firms, the founders prepared presentations and showed them documents, such as early business plans. (Farmwald, Tr. 8100). These meetings occurred around the time of a June 1989 RamBus Business Plan. (Farmwald, Tr. 8100-01; see CX 533). 70. The start-up had significant financial considerations and according to the June 1989 business plan , " RamBus" founders (Michael Farmwald, Mark Horowitz), were able to invest $75 000 in "seed money" and were seeking an additional $1.5 millon in equity investment. (CX 533 at 4). This amount would only fund the company through "the completion of a prototype and to the development of (its) initial DRA vendor partnerships. " (CX 533 at 4). Until it signed with its revenue producing partners, estimated expenses were $100 000 per month. (CX 533 at 5). 71. In March 1990, Rambus Inc. was born after receiving venture capital funding of $1. million from three firms. (CX 545 at 5; RX 81 at 19). Early Business Plan for the Farmwald/Horowitz Inventions 72. As a 1989 draft business plan explained, Farmwald and Horowitz hoped to establish a de facto standard "by offering all interested DRA and central processing unit ("CPU") vendors a suffciently low licensing fee (2%) that it wil not be worth their time and effort to attempt to circumvent or violate the patents. " (RX 15 at 9). 73. Dr. Farmwald explained , " (w)e were going to try and find customers for our parts, big customers, and we were going to try and license all the DRA makers to build our part to supply those customers " which would lead to de facto standardization. (Farmwald, Tr. 8124-25). 74. The founders intended to use a program of phased licensing and promotion of its proprietary RDRA technology in order to convince the industry to adopt its proprietary technology as the industry standard. (Farmwald, Tr. 8297). 75. The plan was for their technology to be an "open standard" ; they refused to license its technology on exclusive terms. (Farmwald, Tr. 8185; RX 25 at 16). 76. An "open standard" in the DRA industry is a standard for which any patents that apply to it are available on reasonable and nondiscriminatory terms. (Bechtelsheim, Tr. 5897; CX 2112 at 190-91 (Mooring Dep. )). 77. Farmwald and Horowitz wanted to avoid what happened to the Sony Betamax, which was hampered in the market by restrictive licensing. (Farmwald, Tr. 8165-66). Instead, their goal was to license the technology "openly and fairly to everybody so everyone is on equal footing with a relatively low royalty." (Farmwald, Tr. 8165-66). 78. Their early business plans indicate that they were aware that it would be necessary early on to charge lower royalties in order to foster acceptance of their proprietary technology. They recognized that there was a "trade-off of royalty size vs. incentive to develop alternatives to their technology. (CX 533 at 14). 79. To ensure that the FarmwaldlHorowitz technology was standardized, i. , that parts from one manufacturer were interchangeable with parts from another manufacturer, the inventors planned to cooperate with their partners (i. , the licensees who would manufacture the devices) to ensure that feedback was propagated to all partners so that everyone would use the same good ideas instead of creating customized parts. (F armwald, Tr. 8148; see RX 82 at 17). 80. Farmwald and Horowitz believed that they had compellng, revolutionary ideas, that their patents would be significant, and that a small royalty would be palatable given the performance leap of the technology. (Farmwald, Tr. 8112- 13). 81. . The key to success for F armwald and Horowitz was that they "had to find a number of high-volume customers and high-volume producers to produce the part so that it became the part that everybody was using" in order for their technology to become a de facto standard. (Farmwald, Tr. 8140; CX 1750 at 1). 82. To this end, the inventions were designed to be produced using existing DRA manufacturing technology. (Farmwald, Tr. 8142-43; RX 82 at 6). The RDRAM Technology 83. Because from the start the founders believed that " (rJoyalties are the lifeblood of Rambus" (CX 2106 at 221 (Farmwald, Dep.)), Rambus placed great importance on promoting and protecting its proprietary technology. The Rambus founders "felt we had a very significant invention. We felt that the only way to protect and to extract value from that invention was to patent it." (CX 2106 at 28 (Farmwald, Dep. )). 84. Rambus saw its proprietary Rambus DRA ("RDRA) technology as offering dramatic improvements over existing memory technology of the time. In 1992 it claimed that RDRA technology "achieves a ten-fold increase in component throughput" and would result in dramatically increasing system price/performance." (R 81 at 3). In addition, Rambus claimed that use of the RDRA technology "assures a smaller system with fewer components, and provides the user with a modular, scalable solution. " (RX 81 at 3). 85. The high-speed chip-to-chip data transfer RDRA technology was intended to be used not only in memory chips themselves, but also to be implemented in other chips including memory controllers, processors, graphics/video chips and other high performance components used in virtually every computer system. (RX 81 at 3). The proprietary Rambus technology was targeted at mainstream applications from consumer digital video products to desktop computers and graphics up to massively parallel computers. (R 81 at 3). 86. The RDRA technology in the early 1990' s included numerous inventions relating to the bus, the interface between the bus and computer chips, and the DRA. The 1992 Corporate Backgrounder makes clear that the Rambus "solution is comprised of three main elements: the Rambus Channel, the Rambus Interface, and the RDRA." (RX 81 at 6). The Rambus Channel refers to the bus, while the Rambus Interface and RDRA refer to other Rambus innovations separate from the bus. (RX 81 at 7). Each of these elements contain a number of independent inventions. (RX 81 at 8- 11). 87. RDRA narrow bus technology contemplates the use of circuitry on the chips at either end of the bus connection to optimize the signals flowing across the connection. (Horowitz, Tr. 8488-90). This circuitry contains high-level logic which implements a protocol for the chip-to-chip information transfer. (Horowitz, Tr. 8489-90). 88. One of the ways that RDRA technology achieves a high-speed data transfer over the narrow bus is through "multiplexing, " which means that the bus can carry different pieces of information at different points in time. (Horowitz, Tr. 8620-21). This aspect of the RDRA interface protocol means that over several clock cycles the bus can carry a combination of address and control and data signals on one or more of the same bus lines. (Horowitz, Tr. 8620- 21; see Rhoden, Tr. 402-03). 89. Another aspect of the RDRA technology is the use ofa "packetized" data transfer protocol. (Horowitz, Tr. 8621; Rhoden, Tr. 403-05). This term means that information is bundled and the bundle may be sent over multiple clock cycles rather than transmitted all at once. (Jacob, Tr. 5465; Rhoden, Tr. 403-04). 90. The RDRA technology also contains various other distinctive aspects, including a clocking system, sometimes referred to as a loop clock, to assist in controllng the synchronization of the data transfer between chips (Roden, Tr. 404; Horowitz, Tr. 8647), and a method of physically packaging the RDRA memory chips so that multiple chips could be vertically mounted on one another to occupy a small space. (Horowitz, Tr. 8623). 91. The RDRA technology was suffciently distinctive that it was widely considered revolutionary" in the industry and was promoted as such by Rambus. (Horowitz, Tr. 8571; Gross, Tr. 2291; Heye, Tr. 3686- 87). The 1990 Business Plan 92. Early Rambus investors were informed that "(t)he primary business of the Ramus Company" would be to license proprietary technology "to manufacturers of DRA chips and microprocessors ; that " (t)he DRA market is . . . highly sensitized to the concept of standardization ; and that market conditions were such that there is "the ability to set world wide standards for the next generation of DRA chips and memory systems. " (CX 533 at 9). 93. The purpose of this early draft of its business plan was to encourage investment by explaining to investors why Rambus s technology would enable Rambus to be successful in the existing and future DRA market. (See generally CX 533 at 9- 10). 94. Investors were told that "the patented RamBus technology. . . has the opportunity to establish a single high performance DRA standard " that in part due to " (t)he DRA industry penchent (sic) for standardization " once the Rambus technology was licensed to "all major vendors " it would be "extremely unlikely that any potential competitor would be able to gain critical mass enough to challenge" Rambus; and that such considerations, including the existence of "strong barriers to entry" restraining "potential competitors " made Rambus an "exceptionally attractive investment opportunity. " (CX 533 at 9). 95. The strength ofRambus s business model depended also on the strength of its technological innovations. Indeed, Rambus s early filed broad patent application and the advantage its technology was seen to enjoy by virtue of being "faster, denser, lower power and cheaper than any other approach" were touted to investors as the most significant barriers to entry for potential, follow-on competitors. (CX 533 at 9). It was the "stiff competition" presented by Rambus innovative technology as well as its marketing strategy of licensing all of the major vendors that it claimed made it less pervious to competitors than other potential investment opportunities. (CX 533 at 9). 96. Rambus hired its first (and to date only) Chief Executive Offcer - Geoffey Tatewho joined Rambus in May 1990. (CX 545 at 5). RDRAM Promotion and Licensing Strategy 97. By November 1990, Rambus had begun its efforts to promote and protect its technology. (CX 535 at 4-5). At that date Rambus had filed for, but not yet obtained, a base patent on its technology (CX 535 at 3) and had entered into license contracts that compelled partners to use Rambus technology patents and trade secrets only for use in RDRA-compatible chips. (CX 535 at 4-5). 98. By June 1992, Rambus had signed technology license agreements with NEC Corp. NEC"), Toshiba Corp. ("Toshiba ), and Fujitsu Laboratories, Ltd. ("Fujitsu ). (CX 543A at 11). By January 1994, Rambus had signed license agreements with Hitachi, Ltd. ("Hitachi"), Oki Electric Industry Co. ("Oki"), Lucky Goldstar, and Intel. (CX 547 at 12). These agreements involved substantial interaction between Rambus and the licensees. (Farmwald, Tr. 8241). 99. In the course of negotiating with DRA manufacturers and others, Rambus encountered resistence to its business model, and specifically to royalties. (CX 711 at 13 , 61). A few systems companies and IC (integrated circuit) companies have had a very negative reaction to our business model. Some believe that it is not ' fair' that we are wanting to charge a royalty on ICs that incorporate our technology. Others believe our royalty wil make ICS incorporating our technology ' too expensive. ' Two specific examples are Sun and Tseng. (CX 543A at 14). 100. Rambus limited the use of its license agreements to so-called RDRA compatible uses only. Most companies accepted this term. Samsung Electronics Co. , Ltd. ("Samsung however, insisted on an agreement without field of use restrictions. (CX 767). 101. In 1994, Samsung recognized that Rambus s inventions could be used in noncompatible Rambus parts, i.e. in parts without Rambus s proprietary bus technology. (CX 767). Moreover, Rambus made it clear to Samsung that Rambus s intellectual property rights were not limited to the RDRA product. (CX 2078 at 116 (Karp, Dep. )). Presentation of the Rambus Inventions to the DRAM Industry Rambus Visits to DRAM Manufacturers and Systems Companies 102. In 1989- , Drs. Farmwald and Horowitz made visits to many DRA manufacturers and systems companies to try to convince them about the benefits of their approach and to get feedback from them. (Horowitz, Tr. 8515). 103. Among the DRA manufacturers that Drs. Farwald and Horowitz visited in 1989- 90 were Texas Instruments, ffM, Toshiba, Fujitsu, Mitsubishi Electric Corp. ("Mitsubishi" NEC, Matsushita Elect. Indus. Co. , Ltd. ("Matsushita ), Micron, and Siemens (whose former semiconductor division is now Infneon Technologies). (Horowitz, Tr. 8515; Farmwald Tr. 8166). 104. Among the systems companies that Drs. Farmwald and Horowitz visited in 1989- were ffM (both a DRA manufacturer and a systems company), Sun Microsystems ("Sun Motorola, Apple Computer ("Apple ), SGI, and Tandem. (Horowitz, Tr. 8515; Farmwald Tr. 8166-67). 105. The response to the early presentations in 1989-90 was "just disbelief' that Drs. Farmwald and Horowitz would be able to achieve a 500 megabit per second DRA data rate. (Horowitz, Tr. 8516). People who listened to these presentations were also skeptical about many ofthe specific features of the technology. For example, it was felt that putting registers on DRA was too expensive for a commodity part and that one could not put a phase locked loop or a delay locked loop on the DRA itself (Horowitz, Tr. 8517). 106. The four inventions at issue in this case were described in these early presentations. For example, one of the early presentations that Dr. Horowitz gave, with slides dated January 31 1990, states that the Rambus interface "allows ' block mode' transfer from an individual DRA with " 1024 byte long blocks supported." (R 29 at 9; Horowitz, Tr. 8518-20). This describes variable block size or variable burst length. (Horowitz, Tr. 8520). 107. The January 31 , 1990 presentation also describes the use of a delay locked loop on the DRA to reduce clock skew. (RX 29 at 33-34; Horowitz, Tr. 8521-22). 108. The January 31 , 1990 presentation also refers to the dual-edge clock or double data rate technque. (RX 29 at 34; Horowitz, Tr. 8522-23). Preparation and Description of the Rambus Inventions Through Various Technical Publications 109. In the 1990-91 period, Dr. Horowitz prepared detailed techncal descriptions of the Rambus technology. (Horowitz, Tr. 8523). These documents were for Rambus s internal use and were also used with customers and potential customers to convince them of the merits of Rambus technology and to help them build it. (Horowitz, Tr. 8523-24). These documents disclose all four ofthe relevant product markets in this case: dual-edge clocking, on-chip DLL programmable CAS latency, and programmable burst length. The May 1990 Technical Description 110. One ofthese techncal descriptions is dated May 7, 1990 and was generated at about that time. (R 63; Farmwald, Tr. 8168-69; Horowitz, Tr. 8524-25). 111. The May 7, 1990 techncal description described all four of the technological features at issue in this case. (Horowitz, Tr. 8525-29). 112. For example, the techncal description described dual-edge clocking in a figure with two input receivers, one clocked by a signal designated "CLK" (clock) and the other clocked by the complement ofCLK (clock bar), a signal that is zero when clock is one and vice versa. (R 63 at 10; Horowitz, Tr. 8525-26). This means that one receiver samples an input when the clock goes high (the rising edge of the clock) and the other when the clock goes low (the fallng edge). (Horowitz, Tr. 8526). 113. The May 7, 1990 techncal description also described a delay-locked loop on the DRA (on-chip DLL feature). (Horowitz, Tr. 8527-28). A figure in the techncal description shows two delay locked loops generating the internal clocks for Rambus s design. (R 63 at 14; Horowitz, Tr. 8527). 114. The May 7, 1990 techncal description also described programmable latency. (Horowitz, Tr. 8528). In the "device registers" section of the document, an "access time" or latency register is listed. (RX 63 at 18; Horowitz, Tr. 8528). "Latency" refers to the time between request and response. (Horowitz, Tr. 8530). The document explains that a fixed value for latency "does not allow for technology improvements " and, consequently, the Rambus system set(s) the time between request and response during system reset." (RX 63 at 5-6; Horowitz Tr. 8530-31). In other words, the value in the access time or latency register would be fixed when the system was started up and probably would not be changed after that time. (Horowitz Tr. 8531). 115. The May 7, 1990 techncal description also described variable burst length. (Horowitz, Tr. 8528-29). The document contains a table showing a variable number of bytes in the block size or burst length depending on the value in the "BlockType" field. (RX 63 at 21; Horowitz, Tr. 8528-29). The November 1990 Technical Description 116. A later Rambus techncal description, dated November 5, 1990, was generated around that time. (R 94; Farmwald, Tr. 8169; Horowitz, Tr. 8535) 117. The November 5, 1990 techncal description was sent to Siemens (now Infneon). (R 99; Farmwald, Tr. 8169-70). 118. The November 5, 1990 techncal description described dual-edged clocking. First the document contains the same figure relating to inputting data on both edges of the clock as in the May 7, 1990 description. (R 63 at 10; RX 94 at 15; Horowitz, Tr. at 8535-36). Second the document shows that the output data is also being transmitted on both edges of the clock. (R 94 at 19; Horowitz, Tr. 8536). 119. The November 5, 1990 techncal description described two alternatives for the DRA clock circuitry. One alternative was to use a phase locked loop. (RX 94 at 45; Horowitz Tr. 8536-37). The other alternative was to use delay locked loops. (R 94 at 46; Horowitz Tr. 8537). 120. The November 5, 1990 techncal description described varable latency using a data delay field in the request packet. (R 94 at 59; Horowitz, Tr. 8537-38). 121. The November 5, 1990 techncal description described variable block size or burst length with a table similar to that in the May 7, 1990 techncal description. (RX 63 at 21; RX 94 at 60; Horowitz, Tr. at 8538). Siemens Responds With a List of Questions About Rambus Technology 122. Both Dr. Farmwald and Dr. Horowitz received feedback from Siemens regarding the November 5 1990 techncal description. (R 102; RX 117; Farmwald, Tr. 8171-72; Horowitz Tr. 8541-42). 123. A fax from K. Horninger of Siemens to Dr. Farmwald, dated December 7, 1990 contained a detailed list of questions relating to the November 5 , 1990 techncal description. 102; Farmwald, Tr. 8171-73). 124. A fax from H.1. Neubauer of Siemens to Dr. Horowitz, dated January 29, 1991 stated "Dear Dr. Horowitz, concerning the RAUS Techncal Description some basic items remained open. In the following we present a list of detailed questions to you which we would like to get answered." (R 117 at 2; Horowitz, Tr. 8542). 125. A number of the questions in the fax that Siemens sent to Dr. Horowitz related to the four features of Ram bus technology at issue in this case. (See RX 117). 126. Question number one in the Siemens fax asked about the details of how eight bits of data would be transmitted by the DRA and relates to Rambus s variable block size feature. (RX 117 at 2; Horowitz, Tr. 8543-44). 127. Question number two in the Siemens fax asked about the implementation of variable latency in the Rambus technology. (R 117 at 2; Horowitz, Tr. 8544). 128. Another question in the Siemens fax referenced Figure 13 on internal page 14 of the November 5, 1990 techncal description. (R 117 at 4). That figure showed dual-edge clocking or double data rate on the output. Dr. Horowitz s understanding was that Siemens s question related to the implementation ofthe double data rate drivers as shown in the November 5, 1990 techncal description. (R 94 at 19; RX 117 at 4; Horowitz, Tr. 8546). 129. Another question in the Siemens fax referenced Figure 28 on internal page 41 ofthe November 5, 1990 techncal description. (RX 117 at 4). That figure shows a delay locked loop and Siemens s question was about the delay locked loop. (RX 94 at 46; RX 117 at 4; Horowitz Tr. 8546). The April 1991 Technical Description 130. A stil later Rambus techncal description was released on April 1 , 1991 and was a more complete version with many more techncal details. (R 130; Farmwald, Tr. 8171; Horowitz, Tr. 8538). 131. The April 1 , 1991 techncal description described dual-edged clocking. (R 130 at 36; Horowitz, Tr. at 8539). 132. The April 1 , 1991 techncal description described using a phase locked loop on the DRA. (RX 130 at 56; Horowitz, Tr. 8539). 133. The April 1 , 1991 techncal description described programmable latency through the use of a "read delay" or latency register. (RX 130 at 94; Horowitz, Tr. 8539-40). 134. The April 1 , 1991 techncal description described variable block size or burst length with the value in a "count" field representing the number of bytes to be transferred. (R 130 at 64; Horowitz, Tr. at 8539). The March 1992 Press Events 135. On March 9, 1992, Rambus held simultaneous events in the Silicon Valley and in Tokyo to publicly announce its technology and its business plan. (Farmwald, Tr. 8182-84; RX 67 at 1). Prior to this date, Rambus had presented its technology to companies on an individual basis and had secured licenses from three ofthe top five DRA manufacturers: Fujitsu, NEC, and Toshiba. (RX 67 at 2). 136. The press release announcing these events stated that Rambus s revolutionary technology would offer a tenfold improvement over traditional DRAs and would solve the memory bottleneck. (R 67 at 1). The press release also described Rambus s business plan as licensing its technology in return for license fees and royalties. (R 67 at 2). By controllng the Rambus interface standard, Rambus would ensure compatibility. (R 67 at 2). The press release also made it clear that Rambus s "open standard" would be "available for license by any IC (Integrated Circuit) company." (R 67 at 2; see also Farmwald, Tr. 8185). 137. At the events, Rambus made available a "Corporate Backgrounder" that provided an overview ofRambus s business strategy and its technology. (R 81; Farmwald, Tr. 8186). The Backgrounder explicitly detailed Rambus s intellectual property strategy: "Rambus Inc. is fully protecting the intellectual property rights of its technology by filing basic, broad patents in all major industrial nations around the world." (RX 81 at 3). 138. Later in this same public document, there are descriptions ofRambus s technology. (R 81 at 8- 11). The Backgrounder states that Rambus s "dramatic performance improvements were achieved through numerous techncal breakthroughs" and then proceeds to describe " (s)ome of the major techncal higWights of the Rambus solution. " (RX 81 at 8). The technology descriptions included the use of dual-edge clocking: " (a)n innovative electrical interface permits the Rambus Channel to operate at 500 Megabytes/second by using both edges of a 250 clock." (RX 81 at 8). Moreover, the technology descriptions explicitly state that Rambus used the on-chip PLL/DLL technology: "(c)lock skew and capacitive loading are minimized by a phase lock loop circuit on board both the master and the RDRA." (R 81 at 8). 139. The Backgrounder also made it clear that Rambus s technology was divided into three distinct elements of the memory system: the Rambus Channel (the high-speed bus); the Rambus Interface (the circuitry that connects a device, such as a controller or DRA, to the bus); and the Rambus DRA (the memory itself). (RX 81 at 7; Farmwald, Tr. 8188-90). 140. The Backgrounder also stated that Rambus s business strategy was to license its technology, work with the licensee to help implement the technology, and to receive fees and royalties in return. (R 81 at 3; see also Farmwald, Tr. 8186-87). 141. Later that year, at the invitation of Betty Prince, a long-time consultant in the DRA industry (prince, Tr. 8970- , 8986-87), Dr. Farmwald and David Mooring of Ram bus published an article in the October 1992 issue of IEEE Spectrum, which gave a brief description of the Rambus technology and stated that the "technology behind the architecture can be licensed for a royalty fee comparable to that for other patented technologies." (R 332 at 1). 142. During the early 1990' s Rambus s business model was well known in the industry. Brett Willams, a JEDEC Solid State Technology Association ("JEDEC") representative for Micron testified that in 1992 , " I knew it was (Rambus sJ business model to patent their technology, and that's how they would gain their revenues. " (Wiliams, Tr. 857). Similarly, Martin Peisl ofInfneon stated that he was aware ofRambus s business model in the early 1990' and expected Rambus to get patents to cover its technology. (Peisl, Tr. 4505). 143. According to Andreas Bechtelsheim, formerly of Sun Microsystems, Rambus made very clear to Sun that it intended to seek patent coverage for all of its inventions and developments, and Rambus explained to various companies, including Sun, that it was seeking patent coverage for its inventions because it intended to obtain revenue or earn revenue through licensing its technology to both memory manufacturers and system manufacturers. (Bechtelsheim Tr. 5819). Press Coverage: The March 1992 Microprocessor Report Article 144. In connection with the public announcement ofRambus s technology and its business plan in March 1992, Rambus provided information to the press regarding Rambus inventions, and numerous articles about Rambus appeared. (RX 1446). 145. Many ofthese articles provided a significant amount of techncal detail. For example, an article entitled "Rambus Unveils Revolutionary Memory Interface" in the March 4 1992 Microprocessor Report describes Rambus s technology in some depth and described three of the four features of Ram bus technology at issue here, as well as aspects of the fourth. (RX 1446 at 22-26). 146. The article states thatthe "Rambus Channel is a 500-Mbyte/s interface, operating with a 250-MH clock and transferring a byte of data on each clock edge" and that a "phaselocked loop on each Rambus device limits clock skew within the chip." (R 1446 at 22 23). 147. The article also states that the "six-byte request packet encodes a 36-bit address, a bit operation code, and 8-bit transfer length count (in bytes). Byte addressing and block sizes of up to 256 bytes are supported." (RX 1446 at 24). 148. The article also notes that "control registers" on the DRA can be used to specify certain parameters. (R 1446 at 23). Rambus s Disclosure of Inventions Through Public Documents The 1992 Marketing Brochure 149. In early 1992, Rambus produced and distributed its first marketing brochure about Rambus technology. (RX 2183; Horowitz, Tr. 8547). The 1992 marketing brochure describes the four features of Ram bus technology at issue here. (Horowitz, Tr. 8547-48). 150. The 1992 marketing brochure states that the "heart of (the Rambus) Interface is high performance PLL (phase-locked-loop) circuitry which provides the clocks for transmitting and receiving Rambus Channel data. " (RX 2183 at 6). 151. The 1992 marketing brochure describes variable burst length, because data transfers could involve a variable amount of data, indicating: " (t)ransfers of 1 to 256 Bytes per Request." (R 2183 at 7). 152. The 1992 marketing brochure describes dual-edge clocking, stating that " ( d)ata effectively transferred on both edges of the clock." (R 2183 at 9). 153. The 1992 marketing brochure describes programmable latency, stating that "the Read Data Packet is returned a time ReadDelay after the Request Packet" and that this delay value is "programmed into the confguration registers of all devices during system initialization. (R 2183 at 11). Publications Describing the First Rambus DRAM 154. The first Rambus DRA was a 4. 5 megabit Rambus DRA produced by Toshiba in the 1991-92 time frame. (Horowitz, Tr. 8548-49). 155. A paper about the Toshiba 4. 5 megabit Rambus DRA was presented at the 1992 Iriternational Symposium on VLSI Circuits (VLSI Circuits Symposium) and published in the proceedings of that symposium. (R 301 at 76-77; Horowitz, Tr. 8552-54). 156. The VLSI Circuits Symposium is held annually and is one of the top two conferences in the world for circuit designers. (Horowitz, Tr. 8552). The "techncal program commttees" of the Symposium read all the papers submitted and choose the better ones for publication at the conference. (Horowitz, Tr. 8552-53). The techncal program commttees for the 1992 VLSI Circuits Symposium that selected the paper about the Toshiba 4. 5 megabit Rambus DRA included representatives from ffM; Texas Instruments; Siemens AG; Sun Microsystems; Intel; Hitachi; Samsung; Matsushita; Mitsubishi; Fujitsu Laboratories, Ltd. ; Sanyo Electric Co. , Ltd. ; Oki; and NEC. (RX 301 at 5). 157. The paper published in the proceedings of the 1992 VLSI Circuits Symposium about the Toshiba 4. 5 megabit Rambus DRA discusses the four features of Ram bus technology at issue in this case. (Horowitz, Tr. 8554). Figure 2 of the paper shows a block size transfer and read latency. (RX 301 at 77; Horowitz, Tr. 8555). Figure 3 of the paper shows double data rate input receivers. (RX 301 at 77; Horowitz, Tr. 8555). The paper also states that " (t)o eliminate skew caused by the internal circuitry, the DRA contains two PLLs." (RX 301 at 76; Horowitz Tr. 8555). 158. At the end of the 1992 VLSI Circuits Symposium, the authors of the top papers were invited to provide a longer version to be published in the Journal of Solid State Circuits. (Horowitz, Tr. 8555-56). The Journal of Solid State Circuits is the most widely read journal for circuit designers. (Horowitz, Tr. 8555-56). The paper about the Toshiba 4. 5 megabit Rambus DRA was selected, and a longer version of that paper was published in the Journal of Solid State Circuits in April 1993. (R 385; Horowitz, Tr. 8556). Presentations of the Proprietary RDRAM Technology and Nondisclosure Agreements 159. Continuing for many years, Rambus pursued a strategy of actively promoting its proprietary RDRA technology to companies that were in a position to manufacture memory chips or related chipsets. Rambus also promoted RDRA to others, including systems companies. (See Crisp, Tr. 2931; CX 543A at 1 , 3 , 7-8). 160. Rambus s efforts to promote adoption of its proprietary RDRA technology included making presentations concerning the proprietary RDRA technology to memory chip manufacturers and other firms. (E.g. CX 2107 at 63 (Oh, Dep.); Bechtelsheim, Tr. 5818- 19; Kellogg, Tr. 5052-53). 161. In connection with such efforts, Rambus commonly entered into nondisclosure agreements that prohibited the firms from disclosing information concerning the proprietary Rambus technology to others without the consent of Ram bus. (Bechtelsheim, Tr. 5818- 19; Rhoden, Tr. 521; Kellogg, Tr. 5052-53). Rambus s presentations often included a discussion of the patent protection Rambus was seeking for its inventions. (CX 2079 at 83 (Mooring, Dep. CX 2111 at 314- 316- 319- , 320- , 322-24 (Tate, Dep. )). 162. In April 1992, Gordon Kelley offfM attended a presentation by Rambus at ffM comparing the proprietary Rambus RDRA technology with Synchronous Dynamic Random Access Memory ("SDRA). (G. Kelley, Tr. 2535). 163. Desi Rhoden was employed at Hewlett-Packard ("HP") when he began to learn about the Rambus technology in the early 90's. (Roden, Tr. 396). Rambus came to HP to give a presentation about its new memory that it was developing. (Rhoden, Tr. 396). The presentation was made pursuant to a nondisclosure agreement between Rambus and HP. (Rhoden, Tr. 521). Although Rambus did not say anything at that presentation about pending Rambus patent applications, Rhoden assumed that Rambus probably did have patent applications. (Roden, Tr. 521). 164. Andreas Bechtelsheim, a Vice-President for technology at Sun (Bechtelsheim, Tr. 5752), was involved in presentations and discussions with Rambus and understood that Rambus had patent rights that covered its proprietary RDRA technology. (Bechtelsheim, Tr. 5828-29; 5841-42). Rambus "made clear (to Bechtelsheim) that they were going to protect any patent on their memory technology because that was their business model." (Bechtelsheim, Tr. 5829). 165. Mark Kellogg, an employee offfM, learned about Rambus technology through a presentation by Rambus to ffM in the early 1990's. (Kellogg, Tr. 5017, 5052-53). 166. Terry Lee, an employee at Micron, learned about Rambus technology in part from a meeting with Rambus held in 1995. (Lee, Tr. 6601-02). Following the meeting, he and a colleague, Kevin Ryan, reviewed selected patent abstracts. (Lee, Tr. at 6607-08). Lee concluded that the patents appeared to apply specifically to the RDRA bus structure. (Lee, Tr. at 6610- 11). In March of 1997, Lee expressed concerns to the JEDEC JC 42. 3 commttee that a double data rate SDRA ("DDR SDRA) presentation "looked like" one of the Rambus patents he had reviewed in 1995. (Lee, Tr. 6956-59). The June 1992 Business Plan 167. By June 1992, Rambus CEO Geoffey Tate transmitted to the Rambus Board of Directors a comprehensive five-year business plan, which, he explained, was based on "inputs from all of the executives." (CX 543A at 1). As reflected in the "Executive Summary" of this June 1992 Business Plan, Rambus s strategy was to: develop a breakthrough technology with high value added in a large percentage of computer, communications, and consumer digital systems products; establish strong intellectual property barriers; . . . to license the technology for integration onto high volume ICs of all major IC companies and to have license fees cover the costs of technology and market development; to establish Rambusas the new interface standard for systems requiring high performance at low cost; . . . to establish a very high profit stream of technology royalties; (and) to continually improve on Rambus Technology through minor and major enhancements. . . . (CX 543A at 3). Rambus Patent Applications The ' 898 Patent Application 168. Rambus filed patent application serial no. 07/510 898 (the ' 898 application) in the United States Patent and Trademark Offce ("PTO") on April 18, 1990. (CX 1451 at 1- Nusbaum, Tr. 1507). The ' 898 patent application included a descriptive portion, called the specification " that was sixty-two pages long, and included fifteen original drawings. (CX 1451 at 3- , 140-50). The ' 898 patent application contained one-hundred fifty claims. (CX 1451 at 64- 125). 169. In connection with the prosecution of its ' 898 patent application, Rambus was issued a communication by the patent examiner at the PTO containing a restriction requirement. (Nusbaum, Tr. 1511). 170. A restriction requirement reflects that the examiner has reviewed the application and determned that the application contains claims describing multiple "independent and distinct inventions. " The applicant is required to elect which of the claimed inventions it wishes to pursue in the application. (Nusbaum, Tr. 1510). 171. The restriction requirement received by Rambus was an eleven-way restriction requirement; Rambus responded by restricting its original application and filing ten divisional patent applications on March 5, 1992, all of which claimed priority based on the filing date of the original ' 898 application, April 18, 1990. (Nusbaum, Tr. 1511- 12; First Set of Stipulations, Stip. 22). 172. Over time, Rambus filed numerous additional continuation and divisional patent applications claiming priority based on the filing date ofthe original ' 898 application. (See First Set of Stipulations, Stip. 22). 173. Prior to June 1996, Rambus filed a total of seventeen continuation and divisional patent applications claiming priority based on the filing date of the original ' 898 application, and had been issued six United States patents on such applications. (First Set of Stipulations, Stip. 22). 174. As of April 2003 , Rambus had fied sixty-three continuation and divisional patent applications claiming priority based on the filing date of the original ' 898 application, of which ten were stil pending. (First Set of Stipulations, Stip. 22). 175. As of April 2003 , at least 43 United States patents had been issued to Rambus from continuation and divisional applications claiming priority to the original ' 898 application. (First Set of Stipulations, Stip. 13). 176. Over time, various of the Rambus continuation and divisional patent applications claiming priority to the ' 898 application embodied changes and amendments to the claims made in the original ' 898 application and came to describe aspects of the original invention. (See, e. Crisp, Tr. 2927-28). 177. The patents that Rambus has asserted against DRA manufacturers have all issued from applications that are continuations or divisionals stemmng from the original ' 898 application and all share a specification with that original application. (First Set of Stipulations, Stip. 22; Nusbaum, Tr. 1513- 14). 178. Pursuant to the "written description" requirement for a patent's validity, the PTO determned that the claims of these patents were supported by the specification of the original 898 application. (Nusbaum, Tr. 1611- 14). The ' 703 Patent 179. Rambus s first United States patent, US. Patent No. 5 243 703 ("the ' 703 patent" issued on September 7, 1993. (RX 425). Rambus disclosed the ' 703 patent to JEDEC during a commttee meeting in September 1993. (First Set of Stipulations, Stip. 11). The ' 703 patent was subsequently added to the "patent tracking list" maintained by JEDEC, where it was described as involving a "Sync Clock." (JX 18 at 18). 180. The ' 703 patent can be traced back to a divisional application of the original ' 898 application. (R 425 at 1; Fliesler, Tr. 8812). 181. The written description and drawings of the ' 703 patent, like all the issued patents that claim priority to the ' 898 application, are substantially the same as the wrtten description and drawings in the ' 898 application. (RX 425 at 1; CX 1451 at 1; Fliesler, Tr. 8812 8817). Thus the ' 703 patent contains the same descriptions oftechnologies as in the ' 898 application and PCT application. (RX 425 at 7, 8, 9, 14- 21; Fliesler, Tr. 8819-20). 182. In addition to listing the original ' 898 application, the ' 703 patent's written description also contains a list ofthe nine other divisional applications stemmng from the ' 898 application that were pending at the time. (R 425 at 11; Fliesler, Tr. 8813- 14). The PCT Application 183. On April 16, 1991 , Rambus filed an international patent application pursuant to the Patent Cooperation Treaty (the "PCT application ). (CX 1454 at 1). 184. The PCT application is identical in all material respects to the ' 898 application. In particular, the PCT application contains the same written description, drawings, and claims as the 898 application. (CX 1451; CX 1454; Fliesler, Tr. 8811). 185. The PCT application was published and made publicly available as of October 31 1991. (CX 1454 at 1; First Set of Stipulations, Stip. 8). Several JEDEC members obtained the PCT application in the early 1990' , including Mitsubishi and ffM. (R 379A at 1; RX 201 at 1). The ' 898 and PCT Applications Describe Numerous Inventions 186. The ' 898 and PCT applications each contain a lengthy disclosure consisting of a sixty-two page written description, fifteen drawings, and one hundred and fifty claims. (CX 1451 CX 1454). 187. The written description of the ' 898 and PCT applications contain numerous headings and subheadings, such as "Device Address Mapping, " " Bus " " Protocol and Bus Operation Retry Format " " Bus Arbitration " " System Confguration/eset " " ECC " " Low Power 3- Packaging, " " Bus Electrical Description " " Clocking, " " Device Interface " " Electrical Interface - Input/Output Circuitry," and "DRA Column Access Modification." (CX 1451 at 18 , 32, 37, 40, 43 , 45 , 47, 54; CX 1454 at 18 , 55). 188. Although the applications describe how an entire system is to be put together, they also describe numerous techncal features that can be used independently of one another and of the system. (Fliesler, Tr. 8788-89). 189. The ' 898 and PCT applications note that, although a preferred implementation ofthe invention contains 8 bus data lines , " (p)ersons skilled in the art wil recognize that 16 bus data lines or other numbers of bus data lines can be used to implement the teaching of this invention. (CX 1451 at 10; CX 1454 at 10). 190. A person of ordinary skill in the art to which the ' 898 and PCT applications pertain would have an electrical engineering degree and at least two to three years of experience in designing computer memory circuits. (Fliesler, Tr. 8779-80; Nusbaum, Tr. 1613). 191. It was Dr. Horowitz s understanding when the patent application was filed that the various solutions to problems described in the application could be used independently of one another. Thus, if one did not want quite the level of performance that Drs. Farmwald and Horowitz envisioned, one could use only a subset of the technques described in the patent application. (Horowitz, Tr. 8514- 15). 192. Dr. Farmwald never thought of his ideas as implementing a "narrow" bus. (Farmwald, Tr. 8143). Rambus originally used a 9-bit wide bus because that corresponded to the number of pins that could fit on the edges of the chips that existed at the time; later Rambus used wider buses because more pins could be placed on the chip. (Farmwald, Tr. 8143-44). Whle some ofthe inventions ofDrs. Farmwald and Horowitz might enable narrower busses to work better, the inventions are not specific to a particular bus width. (Farmwald, Tr. 8144). 193. A March 12, 1993 Mitsubishi memorandum begins by stating that a "need has arisen to evaluate in detail all of the claims in a patent being applied for by Rambus (1 patent, a total number of claims is 150)." (R 2214A at 1). The memorandum goes on to list guidelines for this evaluation, including " 1) Do not discuss Rambus interface. 2) Determne whether or not any other areas contain technologies that wil be important in increasing memory speed in the future. (RX 2214A at 1). 194. A June 10, 1993 Mitsubishi document with the heading "RAUS Patent (summary of responses)" states: " (i)n addition to the technologies of narrower bus width and communication by protocol that are described above, the RAUS patent includes a variety of requirements such as memory system confguration, packaging method, and device confguration and it can be achieved through a combination ofthese factors." (R 406 at 4). The document continues: "(t)he individual technologies that appear in the RAUS patent wil be used independently in the future." (R 406 at 4). Description of Access Time Registers 195. The ' 898 application and the PCT application describe access time registers that store latency, that is the amount oftime between receiving a request and driving data onto the bus in response to that request. (CX 1451 at 16 23; CX 1454 at 16 23; Jacob, Tr. 5481). The applications state that "(e)ach slave may have one or several access-time registers " where "slave can refer to a DRA. (CX 1451 at 16; CX 1454 at 16; Jacob, Tr. 5649). 196. In common use, programmable CAS latency in the mode register of an SDRA is set at initialization. (Jacob, Tr. 5648-49). The ' 898 application and PCT application state with respect to the access time registers (and other registers): " (m)ost of these registers can be modified and preferably are set as part of an initialization sequence." (CX 1451 at 16; CX 1454 at 16). 197. A Mitsubishi document headed "Assessment of Ram bus Patents (Second Half)" states next to the numbers 95 97 and 103: "Modifiable Access Time Register (Similar to SDRA latency control)." (RX 2213A at 25 27). Claim 103 of the PCT application (and ' 898 application) refers to a "modifiable access-time register." (CX 1451 at 104; CX 1454 at 105). 198. In a claim-by-claim analysis of the PCT application produced by Mitsubishi, a marginal note identifies claim 103 of the application as relating to latency and SDRA. (RX 2213A at 7, 9). The analysis further indicates that Mitsubishi determined that this claim relating to latency in SDRAs was particularly important, for Claim 103 was marked "A." (RX 2213A at 7, 9). A later page of the document explains that an "A" grade means that a technology is "important for increasing DRA speed." (RX 2213A at 27). Description of Block Size 199. The ' 898 application and the PCT application describe varying the "block size " that is the amount of data transmitted in response or received in response to a request. (CX 1451 at 29-30; CX 1454 at 29-30; Jacob, Tr. 5477-78). The applications each state that "BlockSize (0:3) specifies the size of the data block transfer. " (CX 1451 at 29; CX 1454 at 29). The applications each contain a table showing the "Number of Bytes in Block" corresponding to the value in the BlockSize" field. (CX 1451 at 30; CX 1454 at 30). 200. "Burst length " as the term is used in SDRAs, refers to the amount of data to be transferred per read or write transaction. (Rhoden, Tr. 379-80; Jacob, Tr. 5396-97.) Likewise block size " encodes the amount of data to be transferred per read or write transaction. (Jacob Tr. 5477). The two terms describe the same function and are used interchangably. (Horowitz Tr. 8661-62; Geilhufe, Tr. 9643). Description of Bus Clock 201. The ' 898 and PCT applications state: " (c)lock distribution problems can be further reduced by using a bus clock and device clock rate equal to the bus cycle data rate divided by two, that is, the bus clock period is twice the bus cycle period. Thus, a 500 MH bus preferably uses a 250 MH clock rate." (CX 1451 at 49; CX 1454 at 50). If clock rate is half the data rate on the bus, both edges of the clock must be used to transmit data. (Fliesler, Tr. 8801-02). 202. Figure 10 in the ' 898 and PCT applications shows two input receivers clocked by clock" and "clock bar" as in the Rambus techncal descriptions. (CX 1451 at 147; CX 1454 at 148; Fliesler, Tr. 8799). If "clock bar" is high when "clock" is low, and vice versa, data is input on both the rising and fallng edges of clock. (Fliesler, Tr. 8799-800). 203. Figure 13 in the ' 898 and PCT applications shows a timing diagram with data being input, as indicated by the arrows along the bottom of the figure, on both the rising and fallng edges of the clock. (CX 1451 at 149; CX 1454 at 150). Howard Sussman, the JEDEC representative for Sanyo and formerly the JEDEC representative ofNEC, testified that Figure 13 of the PCT application shows to him that "input being sampled on the high and low edge of the clock" and that is "double data rate input." (Sussman, Tr. 1322, 1467-68). Description of Variable Delay Circuitry With a Feedback Loop 204. Figure 12 ofthe ' 898 and PCT applications describes variable delay circuitry and a feedback loop. (CX 1451 at 148; CX 1454 at 149; Jacob, Tr. 5649-50). 205. When Joel Karp, then of Sam sung, reviewed Rambus s PCT application in 1991 Figure 12 'jumped out" at him as evidencing a DLL. (CX 2078 at 119 (Karp Micron Dep. CX 2114 at 276-77 (Karp Dep. 206. In its license negotiations with Rambus in 1994, Joel Karp felt that Samsung was motivated to seek a non-assertion provision for non-Rambus-compatible uses ofRambus inventions because of the on-chip DLL shown in Rambus s PCT application. (CX 2078 at 107- , 119-20 (Karp, Micron Dep. )). Review of the ' 898 or PCT Application Should Have Raised Concerns That Rambus Might Be Able to Obtain Claims Over the Four Technologies at Issue 207. A person of ordinary skill in the art or a patent lawyer reviewing the ' 898 application or PCT application would have realized that Rambus might have claims broad enough to cover programmable CAS latency, programmable burst length, dual-edge clocking, and on-chip DLL. (Fliesler, Tr. 8784- , 8810- 11). 208. An experienced DRA designer reviewing the PCT application would reach the conclusion that there is considerable similarity in form and function between programmable latency, variable burst length, dual-edge clocking, and on-chip DLL as described in the PCT application and the corresponding features in SDRAs or DDR SDRAs. (Geilhufe, Tr. 9556- 57). 209. If an experienced DRA designer working on designing an SDRA incorporating programmable latency and burst length in the early 1990's had reviewed the PCT application, he likely would have become concerned that Rambus might have claims to those features and would have raised the issue with management. (Geilhufe, Tr. 9558). 210. A manager faced with this issue, in light of the potential for substantial economic consequences if a DRA design infnges a patent, would likely have gathered additional techncal analysis from specialists and, if there remained a concern, would have taken the issue to corporate counsel for a careful review. (Geilhufe, Tr. 9558-59). 211. When Mitsubishi reviewed the PCT application, it undertook an in-depth study. A March 3 , 1993 Mitsubishi memorandum requests cooperation on evaluating Rambus s PCT patent application because they "realized that the technology is related not only to stand-alone semiconductor devices but also to systems." (R 379A at 1). 212. A June 10, 1993 Mitsubishi document stressed the need for expert analysis of Rambus s patent application to determine the scope of the claims, particularly as to individual technologies disclosed in the patent application: " (t)here is a need to examine the specifications of the patent claims to determine whether individual technologies used independently will infinge on the RAUS patent, and for that we wil have to obtain the views and interpretations of experts. " (RX 406 at 4; see also RX 416A at 1). 213. An August 16, 1993 Mitsubishi document again raised the issue of whether Rambus could have claims on features separate from any particular bus architecture. (RX 419A at 1). 214. A January 11 , 1996 memorandum indicates that Mitsubishi subsequently conducted an "investigation of the US patents owned by Rambus" that were granted by the end of October 1995 and that eighteen patents met that criteria. (R 528A at 1). 215. Mitsubishi also maintained a chart tracking all ofRambus s issued US. patents. For example, one version of this chart begins with Rambus s first issued US. Patent No. 5 243 703 , at number one and concludes with US. Patent No. 5 578 940 which issued on November 26, 1996 at number twenty-seven. (R 2216 at 2 4). Rambus s ' 327 patent is listed at number twentythree on the chart. (R 2216 at 3). 216. A later version of the Mitsubishi chart contains thirty-seven Rambus patents and includes patents that issued in early 1998. (R 2218 at 3-6). 217. A Mitsubishi analysis of the claims of the PCT application specifically calls out the modifiable access time register and notes its similarity to SDRA latency control. (R 2213A 27). 218. An August 24, 1996 report on a Rambus meeting states: "Rambus' patents. Issued: , filed: 80. For example, data is transferred at both edges." (R 756A at 1). 219. As Complaint Counsel concede, Rambus has obtained patent claims that cover programmable CAS latency, variable burst length, dual-edge clocking, and on-chip DLL as those features are used in SDRAs and/or DDR SDRAs. (Complaint ,- 91). Rambus has asserted claims covering these four features against SDRAs and DDR SDRAs. (Complaint ,- 92). il. JEDEC IS A COLLABORATIV STANDARD SETTING BODY FOR THE SEMICONDUCTOR INDUSTRY Early History of JEDEC 220. JEDEC was founded in 1958 and originally named the "Joint Electron Device Engineering Council." (CX 302 at 10; I. Kelly, Tr. 1773-74 ("JEDEC has been active within an EIA organization under the name JEDEC since approximately 1958, and under other names with slightly different functions for a number of years prior to that, probably dating back to the 1940s. )). 221. The current name ofJEDEC is the "JEDEC Solid State Technology Association. (I. Kelly, Tr. 1750-51). 222. Between 1991 and 1996, JEDEC was an activity within the Electronic Industries Association ("EIA") Solid State Products Division, which was itself a division of the EIA' Components Group. (CX 3092 at 14 27; I. Kelly, Tr. 2075). 223. EIA is a "broad-based association that represents the electronics industry in the United States, and it engages in a variety of different activities in support ofthat industry. " (I. Kelly, Tr. 1750; CX 302 at 28). 224. In 1998, EIA changed its name to the Electronic Industries Alliance and JEDEC became a separate division ofEIA. (CX 302 at 11). In 1999, JEDEC became independently incorporated. (CX 302 at 11). 225. Both EIA and JEDEC are headquartered in Arlington, Virginia. (I. Kelly, Tr. 1751). The Purpose and Function of JEDEC 226. JEDEC seeks to create consensus based standards which reflect the interests of DRA manufacturers and exists because of an industry need for standardization. (CX 2767 at 1; I. Kelly, Tr. 1784; Landgraf, Tr. 1685). The Organization of JEDEC Member Companies 227. A company becomes a member of both JEDEC and EIA by completing and submitting an application and paying dues. (CX 601; I. Kelly, Tr. 1801-02; Rhoden, Tr. 294-95). Eligible organizations can become members of JEDEC by joining the EIA Solid State Products Division or by joining JEDEC directly," and paying annual dues. (CX 208 at 7). 228. During the time Rambus was a JEDEC member, dues were paid to EIA. (CX 602 at 6, 7). 229. There was no contractual relationship between JEDEC and Rambus. (I. Kelly, Tr. 2075). 230. During the 1990' , JEDEC had approximately two hundred fifty member companies who sent approximately 1800 individuals to participate in approximately fifty commttees. (I. Kelly, Tr. 1774-75). 231. In 1992, when Rambus joined JEDEC, the membership application stated that: JEDEC Commttee membership is limited to companies and independent entities of companies that (1) manufacture solid state products, or provide related services or equipment, and (2) participate in the United States market." (CX 602 at 2). 232. JEDEC' s membership includes companies from around the world. (Rhoden, Tr. 294 (noting companies from Korea, Germany, Taiwan and Japan); see CX 302 at 8). 233. Membership entitles companies to attend meetings, receive minutes, vote, and receive copies of standards and other publications. (I. Kelly, Tr. 1805-06). 234. Companes not interested in the outcome of a particular issue were encouraged to abstain from voting. (Roden, Tr. 303-04). 235. During the early and mid- 1990' , JEDEC minutes were regularly circulated to all members. (Crisp, Tr. 3139). The minutes were also available in the early 1990's to non-members with the possible exception of a Russian company. (G. Kelley, Tr. 2622-23). 236. JEDEC manual 21-H gives commttee chairs discretion to allow guests to attend meetings: " (a)ll JEDEC Commttee meetings are open to members, their designated alternatives and guests invited by the Commttee. Others may attend meetings only with prior approval of the Chairman. " (RX 1211 at 10). The JEDEC Council, Board of Directors and Offcers 237. Today, the JEDEC Board of Directors is the governing body of JEDEC. (I. Kelly, Tr. 1768; CX 214 at 1 , 14). Prior to 1999, the JEDEC Council was the governng body JEDEC. (I. Kelly, Tr. 1768). 238. Prior to 1998, the JEDEC Council could not unilaterally set or change policies without approval of the EIA Engineering Department Executive Council ("EDEC" ). (See Kelly, Tr. 2078 2105). 239. The chairman ofthe board of directors is elected by JEDEC members. (Rhoden, Tr. 286). 240. The JEDEC chairman is responsible for "the business aspect of JEDEC, trying to make sure that we (JEDEC) have offce space, staff relationships with other organizations, and to make sure that we take care of the business aspects of the corporation itself." (Roden, Tr. 286- 87). 241. Desi Rhoden is the current Chairman of the JEDEC Board of Directors. (Rhoden Tr. 283). 242. John Kelly is the current President of JEDEC. (I. Kelly, Tr. 1750-51). 243. John Kelly has also been the General Counsel ofEIA since 1990. (I. Kelly, Tr. 1754). 244. The EIA General Counsel is "the legal counsel for all of the operating units within EIA, including JEDEC." (I. Kelly, Tr. 1754). The EIA General Counsel is the person responsible for interpreting EIA rules and the JEDEC rules, including the JEDEC patent policy. (I. Kelly, Tr. 1939; Sussman, Tr. 1348-49). 245. Whle the General Counsel may interpret the policies and rules, EDEC establishes what the policies and rules are. (1. Kelly, Tr. 2078). 246. Today, JEDEC employs a staff often persons to facilitate the meetings of JEDEC commttees. (1. Kelly, Tr. 1792-93). During the early to mid- 1990' , the size of JEDEC' s staff was considerably smaller than the current size. (1. Kelly, Tr. 1795). The JC 42 Committee 247. JEDEC is organized into commttees and subcommttees. (Landgraf, Tr. 1687). 248. The members of each commttee or subcommttee elect a chairman. (1. Kelly, Tr. 1794). 249. The JC 42 commttee is concerned with developing standards for memory products. The JC 42 membership consists of "(a)lmost all of the DRA memory companies, SRA memory companies, logic companies, customers of memory, as well as interconnect companies such as socket manufacturers " and testing companies. (Wiliams, Tr. 765-66; Rhoden, Tr. 288). 250. The JC 42 Chairman is responsible for coordinating all the activities in the JC 42 commttee and subcommttees, including the scheduling of meetings. (Rhoden, Tr. 288). 251. The JC 42 commttee had several subcommttees focusing on particular specialized subject matters. (1. Kelly, Tr. 1769; Rhoden, Tr. 285 (JC 42 included subcommttees devoted to DRA (42.3), SRA (42.2), memory modules (42. 5), flash memory and other types of programmable devices)). 252. JEDEC's JC 42. 3 subcommttee develops standards relating to DRA products. (Peisl, Tr. 4381; Rhoden, Tr. 283-84). 253. In late 1991 , approximately forty to fifty companies were represented on the JC 42. subcommttee. (Roden, Tr. 340-41; JX 10 at 1-2). 254. The JC 42 commttee and its related subcommttees typically meet between four and eight times per year. (Roden, Tr. 340). 255. Minutes of JC 42 commttee and its subcommttees are prepared by Ken McGhee, a staff person. (Roden, Tr. 327). There is a review process that goes on before the minutes are made offcial and distributed to members. (Roden, Tr. 591). 256. The minutes of JC 42 and its subcommttees record the key decisions that are made during the standard development process, including motions and votes. (Roden, Tr. 327-28). The minutes were intended to be a chronological statement of the events and occurrences in the meeting, although they were not a transcript. (Rhoden, Tr. 590-91). The Standard Development Process 257. The standard development process begins with discussions among the participants at a JEDEC meeting concernng subjects that members may feel should be considered as possible standards. (Roden, Tr. 406-07). 258. JEDEC entertains a number of proposals by members when working toward a standard for a new device. (Rhoden, Tr. 415). 259. JEDEC members decide which of these ideas to pursue. (Roden, Tr. 415-416). 260. There is a first showing or first presentation when proposals typically receive an item number. (Calvin, Tr. 1025). 261. In some cases, discussions of possible features generate a survey ballot that requests the members to give their views concerning different solutions. (Roden, Tr. 481 , 516). 262. Following the conclusion of the second or subsequent presentations, the commttee decides if it wants to create a ballot to vote on the substance of a proposed standard. (Rhoden Tr. 406-07). 263. JEDEC participants often had significant differences of opinion concerning the development of a standard. These differences of opinion drove heated debates concerning the merits of the various solutions to the techncal challenges facing the JEDEC participants. (E.g., CX 711 at 14; CX 711 at 33; CX 711 at 47; CX 680 at 1; CX 680 at 2; Rhoden, Tr. 434-35 (" you give ten engineers a problem, you ll probably get 12 or 14 solutions, and the same is true inside the discussions inside the commttee )). 264. From time to time, ballots failed or were put on hold in the JEDEC commttees because the commttees did not reach a consensus. (JX 12 at 6, 12; JX 19 at 10; JX 26 at 5). 265. If it preferred, a commttee could pass items individually but place the individual items on hold until an entire list of related items that were needed to define a single standard was complete, and once that group of ballots was complete and passed, then together the commttee could motion them to go to Council for publication. (G. Kelley, Tr. 2554). 266. Afer a JEDEC commttee approves a standard, the proposed standard is sent by a ballot to the JEDEC board of directors, which then has to again by a consensus approve the ballot in order for the proposal to become a JEDEC standard. (1. Kelly, Tr. 1785; Rhoden, Tr. 406-07). 267. JEDEC' s consensus based process means that the board of directors will consider any commttee votes that were cast in opposition to the proposed standard. (1. Kelly, Tr. 1786). 268. JEDEC' s consensus based process often requires years in order to adopt a new standard or change an existing standard. (polzin, Tr. 3977; Peisl, Tr. 4453 ("JEDEC is traditionally a very slowly moving consortium, and there s a reason for that, because there s so many companies involved, it' s basically the whole industry that produces parts for the PC and the laptop and the server business, so to try to reach consensus at JEDEC, based on my experience have been incredibly hard and tough. In the last decade, essentially there were only two standards that emerged for SDR and DDR." )). 269. In order to create common parts that are plug compatible during the 1990' , JEDEC standards became more detailed. (CX 35 at 14- 15; G. Kelley, Tr. 2390). 270. Formal standardization in the DRA industry benefits the entire industry. (Prince Tr. 9016- 17). 271. JEDEC standards are very valuable to manufacturers. (CX 707 at 1 ("JEDEC is a big deal to them (Samsung) because it (JEDEC) represents the big users. ); Peisl, Tr. 4383-84; Bechtelsheim, Tr. 5790). Rambus s Involvement in JEDEC Rambus s Participation in JEDEC 272. The first Rambus employee to attend a JEDEC meeting on behalf of the company was Willam Garrett, who first attended a meeting in early December 1991 at the invitation of Toshiba. (CX 670 at 1). Garrett was later replaced as the Rambus primary representative at the JC 42. 3 Commttee by Richard Crisp, who then became Rambus s representative at JEDEC. (Crisp, Tr. 2929). 273. In February 1994 Rambus renewed its JEDEC membership for the 1994 calendar year and in April 1995 Rambus paid its dues to renew its JEDEC membership for the 1995 calendar year. (CX 602 at 6-7). 274. The final JEDEC meeting attended by Rambus was the meeting in December 1995. (CX 2104 at 853-54 (Crisp, Micron Dep. )). Rambus did not renew its membership for 1996. (CX 887). Rambus Representatives Learn About the EIAJEDEC Patent Policy 275. Jim Townsend, JC 42 Chairman and ffM representative, made a presentation concernng the patent policy and showed the patent tracking list at most JEDEC meetings attended by Crisp. (JX 12 at 5, 28-29; JX 13 at 4; CX 42A at 2; JX 15 at 4; JX 16 at 5; JX 17 at 3; JX 18 at 3 , 15- 18; JX 19 at 4; JX 20 at 4, 15- 18; JX 21 at 4, 14- 18; JX 22 at 3 , 12- 16; JX 25 at 3 , 18-26; CX 88A at 2; JX 27 at 4 20-25). 276. At the May 1992 JEDEC meeting, Chairman Townsend showed a copy of the new American National Standards Institute ("ANSI") patent policy implementation guide and secretary Ken McGhee spoke concerning the EIA patent policies. (CX 34 at 3 , 10- 11; CX 34A at 7). 277. At the September 1993 JEDEC meeting, Townsend showed a draf of portions of the revised JEP 21-I Manual. (JX 17 at 12; see also CX 2092 at 63-64 (Crisp, Infneon Trial Tr.)). The draft stated only that "the commttee Chairperson must have received written notice from the patent holder" that the license would be made available on a reasonable and nondiscriminatory basis. (JX 17 at 12). The draft did not impose an obligation to disclose intellectual property and did not advise the Chairperson to call attention to such an obligation. (JX 17 at 12). Rambus Continued to Stay Abreast of JEDEC and SyncLink Activities 278. The minutes of JC 42. 3 meetings are publicly available. (G. Kelley, Tr. 2623). 279. Several sources provided information to Rambus about JEDEC meetings after Rambus withdrew from JEDEC. (Crisp, Tr. 3413). 280. In 1997, Richard Crisp, Rambus s principal JEDEC representative, received information about JEDEC' s activities from a source called "deep throat." (Crisp, Tr. 3414; CX 929 at 1; CX 932 at 1 (Crisp June 1997 email: "My ' deep throat' (DT) source told me that the DDR bandwagon is moving fast within JEDEC with all companies participating. )). 281. Crisp also received unsolicited information relating to proceedings at JEDEC from an anonymous source called "Mixmaster " a reporter Crisp called the "Carroll contact " and a source known as " Secret Squirrel." (Crisp, Tr. 3414- 17; CX 935 at 1). 282. Crisp shared JEDEC-related information he received from Deep Throat, the Carroll Contact, Mixmaster, and other sources with Rambus executives and engineers. (Crisp, Tr. 3413- 17; CX 935 at 1; CX 929 at 1; CX 973 at 1; CX 979 at 1; CX 1014 at 1). 283. Afer June 1996, Rambus continued to follow SyncLink' s activities. (Crisp, Tr. 3388-89; Crisp, Tr. 3395-96; CX 711 at 183). IV. EARLY DEVELOPMENT AND ADOPTION OF JEDEC DRAM STANDARDS The Initial SDRAM Standard Demand for aNew Generation of Memory 284. "Asynchronous DRA is a term that is used to describe DRAs that are driven off the row address strobe ("RAS") and column address strobe ("CAS") signals where the RAS and CAS actually control the operation of the DRA rather than a clock. (Jacob, Tr. 5394). 285. Page mode and extended data out ("EDO" DRAs) are types of asynchronous DRA. (Sussman, Tr. 1469; Polzin, Tr. 4031). In the late 1980's page mode and EDO DRAs were commonly used in the industry. (Sussman, Tr. 1361). Page mode and EDO DRAs were standardized at JEDEC. (Sussman, Tr. 1362; Prince, Tr. 9020-21). 286. In order to respond to the rising demand for performance and to ensure that the new JEDEC standard would result in common parts that were plug compatible, the JC 42. subcommttee began to standardize certain aspects of DRA performance and design relationships. (CX 35 at 14; G. Kelley, Tr. 2388-91). Prior to that time, JC 42. 3 work had generally focused on standardizing the location of pins, also known as pin-out diagrams. (G. Kelley, Tr. 2388). 287. The JC 42. 3 subcommttee subsequently exceeded those boundaries and began standardizing certain technologies that are unrelated to interoperability. An on-chip DLL, for example, as included in the DDR SDRA standard is not required for interoperability. Rather, as Complaint Counsel's techncal expert, Professor Jacob, explained, the DLL used in DDR SDRAs is transparent to the DRA interface. (Jacob, Tr. 5617- 18). 288. A new generation of memory was needed because the industry anticipated that microprocessor and computer speeds would increase and the industry demanded memory that could operate at the same speeds. (CX 2088 at 291-92 (Meyer, Infneon Trial Tr.)). 289. One option considered by the JC 42. 3 subcommttee was to continue to develop a new generation ofEDO DRAs. (CX 711 at 1). 290. Subsequently, "Burst EDO" was also developed and standardized at JEDEC in mid- 1995. (Wiliams, Tr. 873 , 879-80; RX 585 at 1). 291. Burst EDO failed in the marketplace in competition with SDRA. (Wiliams, Tr. 829). As Dr. Oh ofHyundai Electronics Industries Co. , Ltd. ("Hyundai") testified regarding Burst EDO: "this is enhanced version ofEDO, and we wanted to convince our customers the advantages of this part, but was not accepted by our customers. " (CX 2108 at 236 (Oh Dep. )). 292. JEDEC also began to consider a DRA that had been developed by ffM called High Speed Toggle." (G. Kelley, Tr. 2584-85). High speed toggle is also known as "HST. (G. Kelley, Tr. 2441). 293. According to the definition provided by Complaint Counsel's expert , HST was an asynchronous part. Professor Jacob testified that an asynchronous DRA is one where asynchronous RAS and CAS signals control the operation of the DRA rather than a clock. (Jacob, Tr. 5394). Since RAS and CAS were asynchronous in HST, it follows from Professor Jacob' s definition that HST was asynchronous. (Roden, Tr. 568; Kellogg, Tr. 5173). Indeed, a January 1992 document written by Will Meyer of Siemens states: "ffM presented generic high speed toggle mode in Sep '90 which was asynchronous. " (CX 2431 at 1; Kellogg, Tr. 5173). 294. In HST, ffM proposed to transfer data on both edges of the toggle signal. (Kellogg, Tr. 5173; Sussman, Tr. 1381; Rhoden, Tr. 436-37; CX 2080 at 242 (Karp, Micron Dep. )). Whle some witnesses loosely referred to this toggle signal as a "clock " it was not a free runnng clock like the system clock in a synchronous memory such as SDRA or DDR SDRA. (Roden, Tr. 437; Sussman, Tr. 1471). 295. ffM and Siemens made HST presentations at JEDEC during 1990 and 1991 which were included in survey ballots. (JX 2 at 92; JX 3 at 56-57; JX 3 at 7; CX 316 at 1; CX 314). 296. At the May 9, 1991 JC 42. 3 meeting, the subcommttee passed a motion to ballot the ffM HST presentation. (JX 5 at 12). At the same meeting Siemens also made a HST presentation that was like the ffM HST except it used a G/pin instead of a new toggle pin. (JX 5 at 12). Proposal of a Fully Synchronous DRAM 297. At the JEDEC JC 42. 3 meeting in May 1991 , Howard Sussman ofNEC proposed a fully synchronous DRA to JEDEC for the first time. (Sussman, Tr. 1364; CX 2088 at 272- (Meyer, Infneon Trial Tr.)). 298. It is unclear whether Sussman proposed during his initial proposal to use a single edge clock to input and output data and a programmable mode register to set CAS latency and burst length. (Sussman, Tr. 1365-67 and 1373-75). There was no documentation about the NEC proposal attached to the May 1991 minutes. (See JX 5). 299. In 1991 , Sussman held an unoffcial meeting ofJEDEC members in Boxborough Massachusetts to discuss his synchronous DRA proposal. (Sussman, Tr. 1369-70; CX 20). A report about that meeting prepared by Sussman was intended to provide "a consensus of where we were." (Sussman, Tr. 1370). The description of the features of Sussman s synchronous DRA proposal does not include any mention of a mode register, programmable CAS latency, or programmable burst length. (CX 20 at 1). A report about the Boxborough meeting prepared by Gordon Kelley offfM makes clear that Sussman was proposing afixed CAS latency at this time. (R 173 at 3). Kelley s list ofthe main features of the NEC proposal makes no mention of a mode register or programmable burst length. (See RX 173 at 3). 300. At the JC 42. 3 meeting on September 18, 1991 , the subcommttee voted in favor of the ffM HST technology. There were four no votes and a number of comments. (JX 7 at 8). NEC and Samsung commented that the use of a separate toggle signal can limit speed. (JX 7 at 8). The subcommttee decided to put the ballot on hold until more resolution to the comments could be made. (JX 7 at 9). 301. Also at the JC 42. 3 meeting on September 18, 1991 , Sussman made a second presentation ofNEC's SDRA proposal. (JX 7 at 13 and 160-62; CX 2088 at 276 (Meyer Infneon Trial Tr.)). 302. A number of other companies also presented synchronous DRA proposals at this meeting, including Texas Instruments, Toshiba, and Hewlett-Packard. (JX 7 at 13 , 163-77). 303. At the September 1991 JEDEC meeting, NEC' s second showing of the synchronous DRA proposal does not mention a mode register, programmable CAS latency, or programmable burst length. (JX 7 at 160-62). 304. It was not until October 1991 , at a second unoffcial meeting ofJEDEC members Portland, Oregon, that Sussman s presentation materials indicated that latency and burst length should be programmable. Both programmable CAS latency and programmable burst length are included ina list of key features of the proposed device. (JX 10 at 50; Sussman, Tr. 1373-75). A timing diagram, a version of which had been used by Sussman at the August 1991 non-JEDEC meeting as well as the September 1991 JEDEC meeting, had the following language added to the right-hand column when it was used at the non-JEDEC meeting in October 1991: "Latency is programmable. (Compare JX 10 at 51 with CX 20 at 3 and with JX 7 at 160). 305. Toshiba also made a presentation for a synchronous DRA including programmable CAS latency (JX 10 at 67), causing Howard Kalter offfM to remark that "programmable latency was the cleverest item Toshiba ever created." (R 199 at 2). By this time, Toshiba was a Rambus licensee and was working on the design ofthe first RDRA chip. (Horowitz, Tr. 8548- 49). 306. At the JEDEC JC 42. 3 meeting on December 4- , 1991 (the first JEDEC meeting attended by Rambus), Mark Kellogg offfM made a presentation comparing HST to synchronous DRAs. (JX 10 at 5 and 84; Kellogg, Tr. 5172-73). 307. Also at the JC 42. 3 meeting of December 4- , 1991 , Howard Sussman presented the results ofa non-JEDEC meeting that had been held in Portland, Oregon on October 24, 1991 to discuss high bandwidth DRA. (JX 10 at 4; Sussman, Tr. 1373). The conclusion from that meeting was that a fully synchronous DRA with all signals referenced to a single positive clock edge would best meet system requirements. (JX 10 at 50). 308. At the JC 42. 3 meeting held on February 27- , 1992, NEC, Hitachi, Fujitsu Toshiba, Mitsubishi and Sun all made presentations regarding synchronous DRA devices. (JX 12 at 39, 42, 60, 69, 76, 94, 110). 309. These companies continued to also make presentations regarding asynchronous DRAs that they proposed to develop as well. For example, at the February 1992 JC 42. meeting, Toshiba made two presentations regarding "address compression" for asynchronous DRAs, Fujitsu made a presentation regarding an asynchronous DRA in a new kind of packaging, and NEC made a presentation regarding an asynchronous DRA with a revolutionary pinout." (JX 12 at 11). 310. No further action on HST was taken at the February 1992 JC 42. 3 meeting. High Speed Toggle items continued to be listed, however, on an active items list presented at the February 1992 meeting by the Subcommttee Chairman. (JX 12 at 19; JX 12 at 20). 311. At a DRA Task Group meeting on April 9- , 1992, NEC, Fujitsu, Toshiba Samsung, Hitachi and Mitsubishi presented proposals for a fully synchronous DRA. (CX 34 at , 33-36). 312. At the April 1992 DRA Task Group meeting, ffM proposed a slightly modified version of its HS T technology. (CX 34 at 32; Kellogg, Tr. 5175). 313. Following the April 1992 DRA Task Group meeting, the JC 42. 3 subcommttee decided to pursue a fully synchronous DRA rather than ffM' s toggle mode. (G. Kelley, Tr. 2515). The JC 42. 3 subcommttee also continued to develop various asynchronous DRAs while it was standardizing synchronous DRAs. 314. By the time Rambus attended its first JEDEC meeting in December 1991 , Howard Sussman was reporting the consensus that a "fully synchronous DRA with all signals referenced to a single (positive) clock edge would best meet system requirements. " (JX 10 at 50). 315. The only evidence of consideration of dual-edge clocking that Complaint Counsel presented after this time is HST which actually proposed an asynchronous DRA with output data on both edges ofa "toggle signal." (See CX 2431 at 1; Kellogg, Tr. 5173). Inclusion of Programmable CAS Latency and Burst Length 316. At the JC 42. 3 meeting of December 4- , 1991 , NEC presented the results of a separate meeting in Portland, concluding that the latency of data to the clock and the burst length should be programmable. (JX 10 at 50). 317. At the same meeting, Texas Instruments made a revised presentation of its SDRA proposal that also included programmable CAS latency and programmable burst length. (JX 10 at , 56; Rhoden, Tr. 419-20). 318. Toshiba made a second showing that included programmable CAS latency and burst length. (JX 10 at 67; Rhoden, Tr. 424). Wrap length and burst length are the same thing. (Roden, Tr. 419-20; Willams, Tr. 812- 13; Sussman, Tr. 1374-75). Neither of the "first showings" at the September 1991 meeting included programmable CAS latency and programmable burst length. (See JX 7 at 163-77). 319. The JC 42. 3 Subcommttee considered a number of alternative methods of determning the CAS latency and burst length, including using a fixed burst length, using pins to set the CAS latency and burst length, and using fuses to set CAS latency and burst length. (Rhoden, Tr. 425-34; Kellogg, Tr. 5099- 102 and 5130-31). The alternative methods considered at JEDEC were rejected. Complaint Counsel did not present suffcient evidence to find that they ever made it past the "first showing" stage. (See JX 10 at 5 , 71; Rhoden, Tr. 425-34; Kellogg, Tr. 5099- 102). 320. At the December 1991 JC 42. 3 meeting, Samsung presented a proposal for SDRAs that included fixed CAS latency and burst length. Samsung proposed using a single CAS latency of2 and a single burst length of8. (JX 10 at 71; Rhoden, Tr. 425-28; Kellogg, Tr. 5099- 101). The Samsung proposal also included a fuse option to select between two different burst options. (JX 10 at 71; Rhoden, Tr. 427-28). 321. At the December 1991 JC 42. 3 meeting, Mitsubishi presented a proposal for an SDRA that would use two pins, BT and WP, to set the burst length and burst type. (JX 10 at 74; Kellogg, Tr. 5102). In its proposal, Mitsubishi provided for two burst length options, a burst length of 4 and 8. (JX 1 at 74; Rhoden, Tr. 430-34). The Mitsubishi presentation was designated as a "first time presentation. " (JX 10 at 5). 322. At the December 1991 JC 42. 3 meeting, Texas Instruments presented a proposal using the WCBR cycle to program the mode register to determine burst length and CAS latency. (JX 10 at 50, 56). 323. WCBR indicates a situation where the write signal is low and a CAS signal is sent before the RAS signal. While common in a test or refresh operation, CAS before RAS differs from a normal read or write operation where the RAS would be sent before the CAS. (Kellogg, Tr. 5107-09). 324. At the JC 42. 3 meeting of February 27- , 1992, NEC, Hitachi, Fujitsu, Toshiba and Mitsubishi all made SDRA proposals that included programmable CAS latency and burst length. (JX 12 at 39 , 76, 91 , 94; Sussman, Tr. 1382-83). At the same meeting, Sun presented comments on what features it would like to see included in SDRAs, including programable CAS latency and burst length. (JX 12 at 110). 325. At a DRA Task Group meeting of April 9- , 1992, NEC, Fujitsu, Toshiba Samsung, Hitachi, Mitsubishi and ffM presented proposals that included programmable burst length. (CX 34 at 30, 32-35). 326. At the next meeting of JC 42. 3 on May 7, 1992, the minutes of the April DRA Task Group s meeting were presented to the full JC 42. 3 subcommttee. (CX 34 at 4 and 30-37). 327. At the May 1992 meeting of the JC 42.3 Subcommttee, Samsung, NEC, Toshiba Hitachi and Mitsubishi all made SDRA presentations that included programmable CAS latency and burst length. (CX 34 at 44 , 83 , 85 , 99, 108, 140). 328. At the May 1992 JC 42. 3 meeting, Cray Corporation ("Cray ) gave a presentation that proposed the use of fuses to select between a set of features for a single bank confguration and a set of featurers for a dual bank confguration, where the feature set included inter alia the CAS latency value and burst length value. The Cray presentation was not identified as a first showing in the minutes (see CX 34 at 3- 12), and there is no evidence that it ever progressed to a first showing. (See Sussman, Tr. 1388; Kellogg, Tr. 5103-05). 329. On June 11 , 1992, four SDRA ballots were sent out to all members. (CX 252A at 1). One ballot sought approval for use of a particular implementation of a mode register which was used to program CAS latency and burst length, as well as other features. (CX 252A at 1 , 3; Crisp, Tr. 3075-76; Rhoden, Tr. 448; Willams, Tr. 811- 12). 330. Richard Crisp was present at the July 1992 JC 42. 3 meeting and participated for Rambus in the discussion and the vote on the proposals, including the mode register proposal. (JX 13 at 1 , 9- 10). David Mooring of Ram bus also was present. (JX 13 at 2). Rambus voted " to the proposals. (JX 13 at 9- 10; CX 2112 at 78-79 (Mooring, Dep.)). Rambus comments cited techncal reasons for voting against it. (JX 13 at 9- 11). These were the only votes cast by Rambus for or against any JEDEC proposals. 331. The results of the vote on the mode register ballot were presented at the next JC 42. 3 meeting on July 21 , 1992. (JX 13 at 9- 12; Sussman, Tr. 1393). The initial tally showed fourteen members in support of the proposal, five against and seven abstentions. (JX 13 at 10). Various subcommttee members offered comments, especially with respect to the need for a CAS latency of 4. (JX 13 at 10- 11). Finally, it was agreed to re-ballot the mode register proposal with an optional latency mode of 4. (JX 13 at 11). 332. At the September 16- , 1992 JC 42. 3 meeting, Sun made an SDRA presentation that included programmable CAS latency and burst length. (CX 42 at 39-40). 333. On January 21 , 1993 , the DRA Task Group made minor techncal edits to the NEC mode register that included programable CAS latency and burst length and had previously been balloted as "Proposed Standard for 16M Bit x 4 Sync DRA Mode Register" JC 42. 92- 85 (item 376. 3). The DRA Task Group decided that a re-ballot was not necessary and added the ballot to the pass-hold category. (CX 47 at 3). Presentations of Additional Technologies Low V oItage Swing Signaling 334. During 1992, JEDEC work included a number of presentations that included low voltage swing signaling. At the February 27, 1992 JC 42. 3 meeting, NEC, Fujitsu, Mosaid Technologies Inc. ("Mosaid"), Sun and Intel all made proposals that included low-voltage swing signaling. (JX 12 at 39, 76, 104, 111 , 113; Crisp, Tr. 3045-46). At this same meeting, the JC 42. 3 Commttee discussed GTL technology for use with SDRA. (JX 12 at 36, 56- , 60, 101- , 104, 111). 335. At the April 8, 1992 Special SDRA Task Group meeting, the JC 42. Subcommttee considered SDRA proposals that included low voltage swing signaling. (CX 34 at 32 (ffM), 33 (NC, Fujitsu), 35 (Samsung, Hitachi), 36 (Mtsubishi)). 336. At the May 7, 1992 JC 42. 3 meeting, the Subcommttee considered SDRA proposals that included low voltage swing signaling. (CX 34 at 59 (NC), 122- 123 (Fujitsu)). 337. At the September 16- 171992, JC 42. 3 meeting, the Subcommttee considered Sun 15 meg SDRA specification which included low voltage swing signaling. (CX 42 at 31). 338. Complaint Counsel did not present evidence suffcient to find that these low voltage swing signaling presentations were ever balloted or that they were incorporated into the SDRA standard. Dual Bank Design 339. During 1992 and 1993 , JEDEC work included a number of presentations that included dual bank design. At the February 1992 JC 42. 3 meeting, the Subcommttee addressed the topic of multiple active sub arrays in two presentations (JX 12 at 34, 37) and multibank or dual bank design in other presentations. (See, e. JX 12 at 60). The Subcommittee considered proposals for multibank, or dual bank, design from NEC, Mitsubishi, Fujitsu, and Sun. (JX 12 at , 76, 110). 340. At the May 7, 1992 JC 42. 3 meeting, the Subcommttee considered SDRA proposals that included dual bank design. (CX 34 at 59 (NC), 122- 123 (Fujitsu)). 341. During that meeting, Kelley of ffM, prompted by Meyer of Siemens, asked Crisp whether Rambus might have patent claims that related to dual bank design. (CX 2089 at 130 133-37 (Meyer, Infneon Trial Tr.). "The way how Mr. Kelley formulated the question was: Do you want to give a comment on this?" (CX 2089 at 136 (Meyer, Infneon Trial Tr.)). Rambus declined to comment. (CX 2089 at 136 (Meyer, Infneon Trial Tr.)). 342. At the September 16- 171992, JC 42. 3 meeting, the Subcommttee considered Sun 15 meg SDRA specification which included a dual bank design. (CX 42 at 30 ("The 4M x 4 device is organized internally as two banks. )). 343. Complaint Counsel did not present evidence suffcient to find that these dual bank design presentations were ever balloted or that they were incorporated into the SDRA standard. Auto- Precharge 344. At a number of meetings during the course of 1992, the JC 42. 3 Subcommttee discussed using the auto-precharge technology in the SDRA standard. (February 1992: JX 12 at 37 39 (NC), 76 (Fujitsu), 94 (Toshiba), 108 (Sun); April 1992: CX 34 at 32 (ffM), 33 (NC), 35 (Hitachi); May 1992: CX 34 at 6, 150). 345. At the September 16- , 1992 JC 42. 3 meeting, the Subcommttee considered Sun 15 meg SDRA specification which included an "autoprecharge" option. (CX 42 at 45). Autoprecharge was incorporated as a feature in the JEDEC SDRA 21-C standard, issued in November 1993. (JX 56 at 115). 346. Complaint Counsel did not present evidence suffcient to find that these auto precharge presentations were ever balloted or that they were incorporated into the SDRA standard. Source Synchronous Clocking 347. At the April 1992 JC 42. 3 Special Task Group meeting, the DRA Task Group discussed the issue of source synchronous clocking. (CX 1708 at 2 ("Hitachi brought up the issue of source synchronous clocking. "); Crisp, Tr. 3053-54 (recallng that a discussion on source synchronous clocking had taken place at this meeting)). 348. Complaint Counsel did not present evidence suffcient to find that this discussion of source synchronous clocking was ever balloted or incorporated into the SDRA standard. Externally Supplied Reference Voltage 349. At the February 27, 1992 JC 42. 3 meeting, Samsung proposed an externally supplied reference voltage. (JX 12 at 58; Crisp, Tr. 3043). 350. Complaint Counsel did not present evidence suffcient to find that this presentation was ever balloted or incorporated into the SDRA standard. Adoption of the SDRAM Standard 351. At the JC 42. 3 meeting on March 3- , 1993 , the subcommttee voted unanimously to send 14 SDRA ballots to Council to become approved as a standard for SDRAs intended for publication as Release 4 of the 21-C standard. (JX 15 at 14; JX 16 at 5). The ballots were in fact sent to Council after the vote. (G. Kelley, Tr. 2554-55; JX 16 at 5). 352. The subcommttee agreed to issue a press release stating that the Sync DRA standard has been approved by subcommttee. (JX 15 at 14; G. Kelley, Tr. 2555). A copy of the release was attached to the minutes of the March meeting. (JX 15 at 99). Among the features included in this standard was programmable CAS latency and burst length. (JX 56 at 114). 353. At the JC 42. 3 meeting on May 19- , 1993 , Gordon Kelley offfM reported to the full JC 42. 3 subcommttee that the SDRA ballots had gone to Council and that all council members, apart from AT&T, had supported the ballots. He attached to the minutes a letter responding to AT&T' s concern by proposing additions to the Mode Register. (JX 16 at 5 and 36- 37). G. Kelley also distributed copies of the ballots to the subcommttee. (JX 16 at 5; G. Kelley, Tr. 2557-58). 354. On May 24, 1993 the JEDEC Council formally approved adoption of the standard in Release 4 of the 21-C standard. (CX 54 at 8- 10; G. Kelley, Tr. 2559-60). 355. In November 1993 JEDEC published the SDRA standard as JEDEC Standard No. 21-C Release 4. (JX 56; Wiliams, Tr. 801). The standard included a programmable mode register that includes programmable CAS latency and burst length. (JX 56 at 114; Rhoden, Tr. 456-58; Willams, Tr. 801-03; Sussman, Tr. 1399-400). 356. JEDEC published its standard for SDRA as part of Release 4 of JEDEC Standard 21-C in November 1993. (First Set of Stipulations, Stip. 19). Since 1993 , JEDEC has published several revisions of the JEDEC standard governing SDRAs, JEDEC Standard 21-C. (First Set of Stipulations, Stip. 20). 357. For a manufacturer to produce JEDEC-compliant SDRAs, the standard requires the manufacturer to design and produce SDRAs with programmable CAS latency and burst length on a mode register. (Sussman, Tr. 1399-401). 358. The first published SDRA standard showed a pinout for three different confgurations ofSDRA. (JX 56 at 106). The x4 confguration shown had 11 address lines (AO-Al1), 4 data lines (DQO-DQ3), and 5 control lines (W, CE, RE, S, DQM, and CKE, where CE is equivalent to CAS and RE to RAS). (JX 56 at 106; see JX 56 at 18-22). The remaining pins consist of a clock pin, power pins and "no connect" pins. (JX 56 at 106). The x8 confguration added four data lines. (JX 56 at 106). The x9 confguration added an additional data line, bringing the total number of bus lines to 26. (JX 56 at 106). No confguration of SDRA with more than 26 bus lines is shown in the standard as initially published in November 1993. (See JX 56). Subsequent Proposals: Costs, CAS Latency and SDRAM Lite 359. As late as 1995, asynchronous DRAs continued to make up approximately 97% of the market, with Fast Page Mode approximating 87.2% and EDOs 9. 9% of the market. (Rapp, Tr. 10248). 360. JEDEC members noted that SDRAs were not being produced due to their overhead and yield issues. (JX 27 at 12- 13). 361. JC 42. 3 members showed a continued interest in asynchronous DRAs and at the January 5 , 1995 JC 42. 3 meeting, Micron made a presentation of an asynchronous DRA called Burst EDO that was based upon a page mode DRA. (JX 23 at 69-79; Wiliams, Tr. 821 825- 362. Although Burst EDO was standardized by JEDEC (Willams, Tr. 873 879-80; RX 585 at 1), it failed in the marketplace in competition with SDRA. (Wiliams, Tr. 829; CX 2108 at 236 (Oh, Dep. ) (" this is enhanced version ofEDO, and we wanted to convince our customers the advantages of this part, but was not accepted by our customers. )). 363. Other JEDEC members made proposals aimed at reducing the costs of SDRAs. At the March ' 15 , 1995 JC 42. 3 meeting, TI proposed reducing test cost by making CAS latency of 1 optional. The proposal retained the then-current features of SDRA, including a mode register with programmable CAS latency and burst length. (JX 25 at 14, 107). 364. At the May 24, 1995 JC 42. 3 meeting, TI made a second showing of its proposal to make CAS latency of 1 optional. (JX 26 at 9). The proposal continued to retain a mode register with programmable CAS latency and burst length from the SDRA standard. (JX 26 at 62). A motion to ballot the TI proposal was unanimously accepted. (JX 26 at 9). Crisp sent an email from the meeting stating that "TI would prefer to eliminate the requirement for supporting CAS latency = 1 to reduce cost of speed testing by removing some testing permutations." (CX 711 70). 365. At the September 11 , 1995 JC 42. 3 meeting, NEC made an SDRA Lite presentation that proposed an SDRA with a reduced feature set aimed at saving costs. (Rhoden, Tr. 475-76; Lee, Tr. 6625-27). That proposal suggested using a fixed CAS latency of3 and two burst lengths of 1 and 4. (JX 27 at 13 66; Lee, Tr. 6626, 6629- , 6632, 11 017; Sussman, Tr. 1416- 17; CX 91A at 33). The minutes of the meeting at which the presentation was made confrm that NEC wanted to retain burst length of both 1 and 4 in SDRA Lite. (JX 27 at 13). 366. There was initial support for SDRA Lite at the meeting, with twenty-three members voting that an SDRA Lite standard was needed and four voting against. (JX 27 at 12). It was agreed at the meeting that Desi Rhoden would prepare a survey ballot that JEDEC would issue. (JX 27 at 14). 367. At the JC 42. 3 meeting on December 6, 1995, SDRA Lite was further discussed. (JX 28 at 6; CX 711 at 191-92). The discussion indicated that "PC users" would not be satisfied with a single CAS latency of3. (CX 711 at 191). 368. On January 31 , 1996, there was an interim meeting of JC 42. 3 where results of the SDRA Lite survey ballot were discussed. Included in the discussion was having fixed CAS latency and burst length. (JX 29 at 13 , 14; Lee, Tr. 6630, 6632, 11018- 19). The survey ballot also asked members if they wanted to include auto-precharge in the reduced specification. (JX 29 at 15). The results of the survey ballot indicate that more respondents wanted to retain multiple CAS latency and burst length values than not. (JX 29 at 13). 369. According to Terry Lee of Micron, the SDRA Lite proposal lost support and was abandoned because it was recognized that the cost added in the full SDRA technology was not as great as initially thought and because members were frstrated at the length of time it was taking to get a standard. (Lee, Tr. 6634-35; see also Sussman, Tr. 1416- 17). 370. SDRAs began sellng in volume in 1997, accounting for 33. 5% of the DRAs sold, and became the dominant product in the market in 1998, accounting for 60. 8% of DRAs sold. By that stage, full page mode DRAs had declined to 8. 8% and EDO to 27. 6% of DRAs sold. (Rapp, Tr. 10248-49). DDR SDRAM - The Next Generation SDRAM Work Within and Outside of JEDEC 371. Work formally began on the DDR SDRA standard with a first presentation given by Fujitsu in December 1996. (CX 375 at 1; JX 35 at 6 34-42; Rhoden, Tr. 1197-98). 372. Desi Rhoden was chairman of the 42. 3 subcommttee is currently chairman of the JC 42 commttee and chairman of the JEDEC Board of Directors. (Rhoden, Tr. 1190-91). In 1998 Rhoden was very actively involved in the DDR SDRA standardization process within the JEDEC JC 42 commttee. (Roden, Tr. 1191-92). 373. On March 9, 1998, Rhoden sent an email to Ken McGhee, the JEDEC Secretary, for forwarding to all JC 42 members. (Roden, Tr. 1192-93; CX 375). The email was an effort by Rhoden to recap what had transpired in the DDR SDRA standardization process. (Roden, Tr. 1195). 374. Rhoden s email dates the first presentation to JEDEC of a DDR SDRA proposal as December 1996 and states that the DDR device was being developed "outside of JEDEC" in 1996. (CX 375 at 1). 375. Rhoden s email also states that the decision to "finally get serious" about DDR SDRA was not made until March 1997. (Rhoden, Tr. 1201). "Real, focused, dedicated work" on the DDR SDRA standard did not take place until April 1997. (Roden, Tr. 1202). The DDR SDRA standard did not take "its basic shape" until September 1997. (Roden, Tr. 1202). 376. There is other contemporaneous evidence that work on the DDR SDRA device did not begin, even outside of JEDEC, until the summer of 1996. In an April 1997 presentation Rhoden stated: "DDR & SLDRA were Introduced In JEDEC in Dec 1996." (RX 911 at 3). 377. An ffM presentation on DDR SDRA dated March 17, 1997 notes that "Industry has been working on DDR definition for 6-9 months " that is, beginnng at some point between approximately mid-June and mid-September 1996. (R 892 at 1). Initially, this work consisted of "small supplier consortiums and individual supplier/user meetings." (R 892 at 1). Consistent with Rhoden, the ffM document dates the first "Offcial DDR presentations" at JEDEC to December 1996, referring (again) to the first showing by Fujitsu. (RX 892 at 1). 378. A March 10, 1997 Mitsubishi memorandum regarding "DDR SDRA Specification Plannng History and Recent Trends" confrms that DDR efforts began outside of JEDEC in the summer of 1996. "To counter Intel' s move toward adopting Rambus, eight companies have been meeting once every 2 weeks to quickly plan DDR specifications." (RX 885A at 1). The Mitsubishi memorandum s first mention of JEDEC work relating to DDR SDRA is the first showing by Fujitsu in December 1996. (R 885A at 1). 379. A July 1997 offcial JEDEC ballot form regarding a proposed DDR SDRA pinout states: "DDR SDRAs has been under discussion within JEDEC since September 1996." (R 967 at 1). 380. JC 42. 3 commttee approval of the DDR SDRA standard was made in March 1998, but was not published until 2000. (See CX 375 at 1; JX 57). 381. The DDR SDRA standard received JEDEC Board of Director approval in 1999. (Rhoden, Tr. 743). 382. The first time that a balloted item was approved as part of the JEDEC DDR SDRA standard was June 1997. (CX 375 at 2). Future Synchronous SDRAM Features 383. Despite detailed minutes taken at each JEDEC meeting about what presentations were made and what topics discussed, there is little evidence regarding any discussion of "next generation SDRA until late 1995, when a "Future Synchronous DRA (SDRA) Features survey ballot was issued. (See CX 260 at 1). 384. Complaint Counsel presented a March 1995 email from Crisp which quotes Wiggers, a JEDEC representative from Hewlett-Packard, as saying that JEDEC had been working for over two years to standardize a high-speed interface. (CX 711 at 54). In the next line Crisp states that " (t)his servers (sic) to further underscore the fact that the JC 16 commttee (led by Farhad Tabrizi ofHyundai) is not delivering on its responsibilities." (CX 711 at 54). Thus Wiggers s statement was in reference to the work of JC 16 not in reference to some undefined new kind of SDRA within the JC 42. 3 subcommttee. (Crisp, Tr. 3520-21). 385. The testimony of Peter MacWiliams ofIntel, who testified that he "first heard about DDRin ' 95" (MacWillams, Tr. 4815), says nothing about JEDEC. MacWillams may have been referring to what Rhoden had described as "private and independent work outside of JEDEC for most of 1996 . . . . " (CX 375 at 1). 386. Moreover, since the JEDEC future SDRA survey ballot was not issued until late 1995, with the results not presented at JEDEC until December 1995, it is unlikely that MacWillams was aware in any JEDEC-related context, prior to that time, of what features might be in a next generation standard. (See CX 260; JX 28 at 6). Presentation of Programmable CAS Latency and Burst Length 387. In October 1995, JEDEC staff distributed to subcommttee members, including Rambus, a survey ballot requested at the September 1995 JC 42. 3 meeting. (CX 260). The subject ofthe survey was "Future Synchronous DRA (SDRA Features." (CX 260 at 1). The ballot asked whether members thought it important to add any additional latency values to those already available. (CX 260 at 9). 388. The results of the SDRA Features Survey Ballot that had issued on October 30 1995 were talled at the same meeting on December 6, 1995. (JX 28 at 36-48). Mosaid made a presentation on the results of the survey. (JX 28 at 6). The CAS latency portion of the survey results showed that JC 42. 3 members strongly supported adding into the mode register CAS latencies in excess offour. (JX 28 at 42). 389. At the March 20, 1996, JC 42. 3 meeting, the RA features and functions subcommttee made a presentation that included use of programmable CAS latency and burst length. (JX 31 at 64). 390. At the June 5, 1996, JC 42. 3 meeting, two presentations were made by Oki on behalf of EIAJ that included programmable CAS ' latency and burst length. (JX 33 at 7, 41-46 and JX 33 at 47-49). The presentations for 100- 150 MH SDRA included three required burst length values and four required CAS latency values. (JX 33 at 41 48). 391. At the September 10, 1997 JC 42. 3 meeting, the subcommttee voted unanimously to send a DDR mode register to Council. (JX 40 at 7-8; Lee, Tr. 6640-41). That mode register included programmable CAS latency (CX 234 at 150; JX 57 at 12; Lee, Tr. 6641) and burst length (CX 234 at 150; JX 57 at 12). 392. The mode register was approved by Council and included in Release 9 of the 21- standard published by JEDEC in August 1999 and subsequently in the consolidated DDR SDRA Specification (JESD79) that was published by JEDEC in June 2000. (JX 57 at 12). Discussion of PLLIDLL 393. There was recognition in the mid- 1990' s among JEDEC members that, as bus speed increased, an on-chip PLL or DLL would become necessary. (Soderman, Tr. 9408- 10; Rhoden Tr. 546). 394. PLLs are similar to DLLs in that they can be used for similar purposes in some applications. (Jacob, Tr. 5617). They are, however, different types of circuits: a PLL uses a voltage controlled oscilator while a DLL uses variable delay lines. (Jacob, Tr. 5616- 17). 395. Rhoden testified that the JEDEC subcommttee members used the terms PLL and DLL interchangeably. (Rhoden, Tr. 492). Once JEDEC chose a DLL, the contemporaneous evidence shows it was always referred to as a "DLL " never as a "PLL." (See, e. g., CX 234 at 176). 396. When Rambus first presented its technology to DRA manufacturers in the 1989- 90 time frame, many felt that it was not possible to put a PLL on a DRA. (Horowitz, Tr. 8517). As late as 1997, well after Rambus had proven that PLLs and DLL could be placed on DRAs and very high data transfer rates achieved, many DRA manufacturers remained daunted by the diffculties involved. In a November 1997 email, for example, Hans Wiggers of Hewlett-Packard explained that DLLs would be "essential" for the data rates that they hoped to achieve, while recognizing that "I know everyone is afraid ofDLLs." (RX 1040). 397. At the September 13- , 1994 JC 42. 3 meeting, NEC made a presentation regarding PLLs on SDRAs. NEC's presentation showed an on-chip PLL circuit and proposed to include a PLL-enable bit in the mode register in order to enable on-chip PLLs. (JX 21 at 87, 91 , 92; Rhoden, Tr. 466; G. Kelley, Tr. 2569-70). 398. As both Complaint Counsel's techncal expert and Rambus s techncal expert made clear, PLLs and DLLs are implemented differently - the former uses a voltage controlled oscillator, while the latter uses variable delay lines. (Jacob, Tr. 5443 , 5617; Soderman, Tr. 9401). 399. In October 1995, JEDEC staff distributed to subcommttee members, including Rambus, the survey ballot requested at the September 1995 JC 42.3 meeting. (CX 260). The subject of the survey was "Future Synchronous DRA (SDRA) Features." (CX 260 at 1). Question 3. 1 asked members whether they believed that use of an on-chip PLL or DLL was important to reduce the access time from the clock for future generations of SDRAs future generations of DRAs. (CX 260 at 12). 400. At the JC 42. 3 meeting of December 6, 1995 , the tally of the votes cast in the Future SDRA Features Survey Ballot was announced. Eleven members voted "yes" and four members " to the question as to whether their company believed that "on chip PLL or DLL is important to reduce the access time from the clock for future generations of SDRAs. " (JX 28 at 45). Onchip PLL/DLL was included among issues with "strong support" in the conclusion of the SDRA Feature Survey Ballot. (JX 28 at 35). 401. Mosaid presented the results of the survey. In response to a question from Hyundai Electronics Industries ("Hyundai"), Mosaid disclosed a pending patent application with claims relating to on-chip DLL technology, but stated that the patent likely to result from the application may not be necessary to use a standard but rather would be an implementation patent. (JX 28 at 6; CX 711 at 192). Mosaid agreed to comply with the patent policy if the patent ends up as a concept patent " not if it ends up as an "implementation patent." (CX 711 at 192). 402. At the January 31 , 1996 JC 42. 3 interim meeting, Micron presented a proposal discussing the potential use of on-chip PLL/DLLs and echo clocks in Future SDRAs. (JX 29 at 17). Micron proposed using a single PLL on the controller or clock chip and echo clocks rather than on-chip PLLs. (JX 29 at 18; Rhoden, Tr. 487). 403. At the JC 42. 3 meeting of March 20, 1996, Desi Rhoden, on behalf of the JC 42. RA Features and Functions Letter Commttee, made a presentation that included on-chip PLL/DLL. (JX 31 at 64; Rhoden, Tr. 492). The presentation provided information regarding what features might be required in the future and confrmed the general knowledge that to achieve high data transfer rates, an on-chip PLL or DLL would be required. (JX 31 at 64). 404. Samsung also made a future SDRA proposal that included discussion of alternatives to on-chip PLL/DLL. (JX 31 at 68-72; Rhoden, Tr. 513- 14; Lee, Tr. 6691). The Samsung presentation related to "alternatives to on-chip PLL/DLL" as it proposed a PLL on the memory controller. (JX 31 at 71)). 405. During the course of its work relating to what ultimately became the DDR SDRA standard, the JC 42. 3 subcommttee also considered, as an alternative to on-chip PLL/DLL, the use of verner circuits. (JX 36 at 58, 64; CX 367 at 3; Kellogg, Tr. 5168). 406. During the course of its work relating to what ultimately became the DDR SDRA standard, the JC 42. 3 subcommttee also considered, as an alternative to on-chip PLL/DLL, the use of an edge-aligned, bi-directional data strobe. (CX 368 at 1 4; CX 370 at 2 3; CX 2713 at 2). Although DDR SDRAs have a "bidirectional data strobe (DQS)," they still use a DLL to align the strobe with the clock. (JX 57 at 5). 407. By the time of the JC 42. 3 meeting of December 9- , 1997, the subcommttee had decided to include an on-chip DLL in the DDR standard that could be turned on or off (Lee, Tr. 6680-81). At this meeting the subcommttee discussed the timing of a device where the on-chip DLL was disabled or enabled. (JX 41 at 18; Lee, Tr. 6680-81). Consideration of Dual Edge Clocking 408. Dual edge clocking can refer to a number of technologies and implementations and is not limited to capturing data off both edges of the clock. (See Lee, Tr. 6688). 409. In a DDR SDRA, the clock is all but ignored during writes to the DRA; the DRA samples incoming data not with respect to the system clock, but with respectto another signal known as the DQS data strobe. (Jacob, Tr. 5642). 410. In a DDR SDRA read operation, data is driven by a data strobe which is not a clock." A "clock" is a "free-runnng" signal, that is runnng all the time, while the data strobe in DDR SDRAs is not free-runnng. (Macri, Tr. 4634). 411. ffM and other JEDEC members made further High Speed Toggle ("HST" proposals in 1990 and 1991. (G. Kelley, Tr. 2584-85). HST did not transfer data on both edges of the clock signal, but instead on both edges of a "toggle" signal. While some witnesses loosely referred to this toggle signal as a "clock " it was not a free runnng clock like the system clock in a synchronous memory such as SDRA or DDR SDRA. (Roden, Tr. 437; Sussman, Tr. 1471). 412. At the JC 42. 3 Subcommttee meeting held on December 4- , 1991 , Mark Kellogg offfM made a presentation comparing High Speed Toggle to synchronous DRAs. (JX 10 at , 84; Kellogg, Tr. 5172-73). 413. Although ffM held patents on HST (G. Kelley, Tr. 2715), there is no evidence that they disclosed them in connection with DDR SDRA. 414. At a special meeting of the JC 42. 3 Subcommttee Task Force held on April 14 1992, ffM proposed a "slightly modified version of its HST technology." This proposal was for an asynchronous DRA. (CX 34 at 32). 415. At a meeting of the JC 42. 3 subcommttee held on May 24, 1995, Hyundai, Texas Instruments and Mitsubishi all made presentations relating to the SyncLink technology. (JX 26 at 10- , 95- 112). 416. In October 1995 , JEDEC staff distributed to subcommttee members, including Rambus, a survey ballot requested at the September 1995 JC 42. 3 meeting. (CX 260). The subject of the survey was "Future Synchronous DRA (SDRA Features." (CX 260 at 1). Question 3. 4 asked members whether they believed future generations of DRAs could benefit from using both edges of the clock for sampling inputs. (CX 260 at 12). This question related to dual edge clocking. (Calvin, Tr. 1033; Lee, Tr. 6689). 417. At a meeting of the JC 42. 3 Subcommttee held on December 6, 1995, the results of the survey ballots were tabulated and announced. No clear consensus on the proposed use of dual edge clock in the next generation standard was reached, with seven members responding that the next generation of SDRAs would benefit from using dual-edge clock technology and nine members responding that it would not. (JX 28 at 45). Two specific comments relating to dual edge clock technology were recorded in the results of the survey ballot, both supportive of using the technology. (JX 28 at 45). 418. At a meeting of the JC 42. 3 Subcommttee held on March 20, 1996, Samsung made a presentation proposing to use dual edge clock technology in the future SDRA standard. (JX 31 at 71; Rhoden, Tr. 512; Calvin, Tr. 1035; Landgraf, Tr. 1719-20; G. Kelley, Tr. 2581-82; CX 2114 at 85 (Karp, Dep. )). There is no evidence that the Samsung presentation ever progressed any further. 419. At the same meeting in March 1996, JEDEC considered runnng a single-edged clock faster in order to double the data rate. (Roden, Tr. 542-43; see JX 31 at 64). Rhoden presentation was not a proposal for a device; it simply provided information regarding what features would be required in the future if certain clock speeds were eventually implemented. (Rhoden, Tr. 542-43; see JX 31 at 64). 420. During the course of its work relating to what ultimately became the DDR SDRA standard, the JC 42. 3 Subcommittee also considered, as a possible alternative to dual edge clocking, the use ofasingle edged clock. (CX 371 at 3; Lee, Tr. 6710- 13). 421. At the September 10, 1997, JC 42. 3 meeting the subcommttee voted to send a ballot including using both edges ofa data strobe to Council. (JX 40 at 8; Lee, Tr. 6714- 15). 422. In 1999-2000, JEDEC considered the possibility of interleaving SDRA chips on the module in order to double the data rate. (CX 150 at 109- 17). In December 1999, Kentron Technologies, Inc. ("Kentron ) made a proposal to JEDEC to interleave SDRA chips on the module. (CX 150 at 115). Subsequent Proposed Features Externally Supplied Reference V oItage 423. At the May 1994 JC 42. 3 meeting and the March 1995 JC- 16 meeting, there were presentations regarding externally supplied reference voltage. (CX 711 at 25 27; CX 711 at 52 54). 424. Some SDRA pinouts included an optional VRF pin, making it clear that an externally supplied reference voltage was not required for the SDRA standards; DDR SDRA pinouts contain a VRF pin. (Lee, Tr. 11035). Source Synchronous Clocking 425. During the March 15, 1995 JC 42. 3 meeting, Crisp recorded a Fujitsu representative s suggestion that it would be necessary to use two clocks, a clock-in and clock-out for high speed operation. (CX 711 at 58). In an email Crisp stated , " (i)t appears that they are starting to figure out that we have a very good idea with respect to source synchronous clocking. Of course they may get into patent trouble if they do this. " (CX 711 at 58). 426. JEDEC included a bidirectional data strobe, or DQS strobe, as part of the DDR SDRA standard. (CX 234 at 164). The data strobe might be considered to be a form of source synchronous clocking, but it is not a well-defined technology. (Lee, Tr. 6682). Adoption of the DDR SDRAM Standard 427. In August 1999, JEDEC issued Release 9 of the 21-C standard. (CX 234). 428. Users requested that JEDEC take everyhing that related to DDR out of Release 9 and put it in a separate specification. (Roden, Tr. 1293-94). In response to user requests JEDEC took all of the DDR specifications that had previously issued in Release 9 ofthe 21- standard (CX 234) and put them together in one document. (Roden, Tr. 1293-94). That document, entitled "Double Data Rate (DDR) SDRA Specification" and numbered "JESD79" was published in June 2000. (JX 57; Rhoden, Tr. 1293-94). 429. Apart from the possibility of some slight updating and clean-up, JESD79 contains the same DDR related material as in Release 9 ofthe 21-C standard. (Roden, Tr. 1294). Features Incorporated into the Standard 430. The DDR SDRA Standard incorporated in Release 9 of21-C and JESD79 included many features that had been previously adopted in the first generation SDRA standard as well as new features such as dual edge clocking and on-chip DLLs. (Sussman, Tr. 1428-29; McWiliams, Tr. 4822; Bechtelsheim, Tr. 5871-72; CX 2451 at 20). On-Chip DLL 431. The DDR SDRA standard utilizes the use of on-chip DLLs. (CX 234 at 176; CX 234 at 197; JX 57 at 8; Lee, Tr. 6643; Rhoden, Tr. 564). Dual Edge Clocking 432. The DDR SDRA requires a particular implementation of dual edged clocking in which read data is aligned with the rising and fallng edges of the clock, but write data is not. The JESD79 DDR SDRA specification covers SDRAs that have dual edge clocking. (JX 57 at 5, 21; Sussman, Tr. 1427; Kellogg, Tr. 5172). Programmable CAS Latency and Burst Length 433. The DDR standard requires a particular implementation of programmable CAS latency and burst length according to which these values are programmed in specific bits of a mode register. (CX 234 at 150; Geilhufe, Tr. 9742-44; Lee, Tr. 6625). In June 2000, JEDEC published a Double Data Rate (DDR) SDRA Specification (JESD79), which was unique to DDR SDRA. It continued to include a programmable mode register to define CAS latency. (JX 57 at 12). Interoperability: The Effect of JEDEC' s Specifications versus Manufacturers' Specifications 434. The JEDEC SDRA and DDR SDRA standards determined what features were required to be present in JEDEC compliant DRAs. (Peisl, Tr. 4384). 435. The JEDEC SDRA and DDR SDRA standards were sometimes insuffcient to ensure interoperability, forcing other industry participants, primarily Intel, to issue specifications used by the DRA manufacturers in place of the JEDEC standards. (MacWiliams, Tr. 4908-09; see also Krashinsky, Tr. 2814- 15). RAMLINK AND SYNCLINK, THE SYNCLINK CONSORTIUM, INTEL AND DRAM MANUFACTURERS 436. In addition to the Rambus and JEDEC efforts to develop standards for next generation DRA technology, there were other similar efforts during the 1990' s. Among these were the Ramlink, SyncLink and SyncLink Consortium efforts, which did not result in commercially viable DRA standards. (F. 437-86). The IEEE RamLink and SyncLink Working Groups The IEEE Membership Requirements and Lack of Patent Disclosure Obligations 437. The Institute of Electrical and Electronic Engineers, Inc. ("IEEE") was a professional organization that engaged in various activities, including standard setting activities. (Tabrizi, Tr. 9117; RX 668 at 2; RX 2011 at 1). 438. Membership in the IEEE was not by company; rather, individuals belonged to IEEE in their individual capacity. (Tabrizi, Tr. 9117; RX 579). There was significant overlap between IEEE and JEDEC, including, for example, individuals from five companies attended both the August 21 , 1995 IEEE 1596. 6 meeting and the September 11 , 1995 JEDEC 42. 3 meeting. (First Set of Stipulations, Stip. 21). 439. The IEEE procedures did not impose any obligation on companies with respect to patent disclosure. (Tabrizi, Tr. 9122; Crisp, Tr. 3283-84; JX 27 at 26). RamLink Was Developed to Standardize a New Future Memory Bus 440. RamLink was being developed by the 1596.4 working group within the IEEE. (Gustavson, Tr. 9280). According to a trip report regarding the February 22, 1995 Ramlink II Working Group, "(t)he Ramlink concept is to use super high speed serial link to transfer the memory (not necessary DRA data to processor." (R 535 at 1). 441. RamLink developed as an effort to standardize a new generic bus to which one could connect any kind of memory. (Tabrizi, Tr. 9117). 442. IEEE was balloting the RamLink proposal for standardization as of June 1995. (Gustavson, Tr. 9283). The IEEE SyncLink Project manated From and Modifed the Proposed RamLink Standard 443. SyncLink developed as a subset of RamLink. (Tabrizi, Tr. 9117; Gustavson, Tr. 9280-82). Whereas RamLink was intended to be a generic bus to which one could connect any kind of memory, SyncLink was intended to be specific to synchronous DRAs. (Tabrizi, Tr. 9117) . 444. The SyncLink project thus modified the RamLink protocol. (Gustavson, Tr. 9284; see also RX 589 at 1). The resulting SyncLink architecture was partially multiplexed; command and address information were sent on a single bus, but data was sent on a separate bus. (Tabrizi Tr. 9119). 445. RamLink consisted of a high speed bus protocol that permtted access, based on scheduling of events, to the bandwidth that already existed inside DRAs. (JX 26 at 95). 446. Richard Crisp attended some of the meetings of the IEEE RamLink and SyncLink working groups. (Crisp, Tr. 3528; RX 579 at 6; RX 590 at 3). Presentation of the RamLink/Synclink Architecture at JEDEC Rambus Elects Not to Comment On Its Intellectual Propert Position 447. In May 1995, Hyundai, Texas Instruments, and Mitsubishi presented the RamLink and SyncLink architectures at JEDEC. (JX 26 at 10- , 95- 113). The Mitsubishi presentation of SyncLink included a description of dual edge clocking. (JX26 at 112; Rhoden, Tr. 471-72; Kelley, Tr. 2574-75; Sussman, Tr. 1408-09). 448. Gordon Kelley asked whether any companies had patent issues regarding SyncLink. (CX 711 at 72). 449. When Crisp, the Rambus JEDEC representative, did not respond to this inquiry at the May 1995 meeting, Kelley asked Crisp to go back to Rambus and then report back to the Commttee whether Rambus knew of any patents, especially Rambus patents, that may read on the SyncLink technology. (CX 711 at 73; Crisp, Tr. 3267-68). 450. At the September 1995 meeting of the JEDEC Commttee, Crisp provided the Commttee a letter from Rambus stating "Rambus elects not to make a specific comment on our intellectual property position relative to the SyncLink proposal" and that " (0 Jur presence or silence at commttee meetings does not constitute an endorsement of any proposal under the commttee s consideration nor does it make any statement regarding potential infngement of Rambus intellectual property." (CX 829). Richard Crisp Indicates That the SyncLink Proposal May Infringe Rambus Patents But Declines To Comment Regarding Rambus Intellectual Propert 451. In June 1995 , Reese Brown posted a copy ofthe ballot for the proposed IEEE RamLink standard on the JEDEC reflector. (CX 711 at 76-77). 452. Thereafter, Crisp wrote an email to Brown stating in part that the proposed IEEE standard had patent issues associated with it. (CX 711 at 79-80; Crisp, Tr. 3282-83). Brown forwarded Crisp s email to Hans Wiggers, the Chairman of the RamLink working group as of mid- 1995. (Crisp, Tr. 3283; Gustavson, Tr. 9282). 453. Wiggers wrote to Crisp because, as Chairman of the RamLink working group, he took Crisp s comment about patent issues "very seriously." (CX 711 at 90-91; Wiggers, Tr. 10595). Wiggers stated that he assumed Crisp had attended the IEEE working group meetings in good faith " and if Crisp knew of any way in which the proposed RamLink standard violated patents held by Rambus or others, he thought Crisp had a "moral obligation" to bring to his attention information about which patents were being violated. (CX 711 at 90-91; Crisp, Tr. 3284-86). 454. Crisp replied to Wiggers by email: Regarding patents, I have stated to several persons that my personal opinion is that the RamlinkSynclink proposals wil have a number of problems with Rambus intellectual property. We were the first out there with high bandwidth, low pincount; DRAs, our founders were busily at work on their original concept before the first Ramlink meeting was held, and their work was documented dated and filed properly with the US patent offce. If you want to search for issued patents held by Rambus, then you may learn something about what we clearly have covered and what we do not. But I must caution you that there is a lot of material that is currently pending and we wil not make any comment at all about it until it issues. (CX 711 at 104-05). 455. Wiggers wrote to Crisp again in July 1995 , stating that as part of submitting the RamLink standard to the IEEE Standards Board, he had to certify that there were no patent issues outstanding. He stated that he had to report his previous communications with Crisp. (CX 711 at 130-31; Crisp, Tr. at 3291-92). 456. Wiggers ultimately related to the working group only a short statement to the effect that Crisp expressed a personal opinion that the SyncLink proposal may infnge Rambus patents that date as far back as 1989. (CX 711 at 146; see also Crisp, Tr. 3296-97). 457. The Secretary ofthe SyncLink Consortium, Dr. Gustavson, and two other engineers subsequently undertook to review the claims in Rambus' s pending patent applications and came to the conclusion that the SyncLink device would infnge those patents, if they issued. (Gustavson, Tr. 9286-87). 458. The IEEE thereafter requested that the 1596.4 working group redesign the RamLink standard so that it wouldn t violate any Rambus patent claims. (Gustavson, Tr. 9296-97). 459. Afer Gustavson reviewed the claims of certain ofRambus s pending patent applications, he concluded that there was no way to work around the claims that he saw, since they related to things that the working group had been doing for ten years or so. (Gustavson, Tr. 9286-87). Nevertheless, Gustavson thought the Rambus patent claims should not block the balloting of the proposed RamLink standard. (Gustavson, Tr. 9294). 460. Gustavson concluded , " (w)e discussed the situation re patents in general, and seem to be in agreement that standards ought to make no assurance to the eventual user that no patent conficts are involved, . . . because that is impossible. Firstly, the writers may not become aware of conficting patents until long after the standard is finished, due to the various pipeline delays and imperfect communication. As far as I could tell, Crisp and Rambus s positions were entirely reasonable in this regard, and so I expect they won t try to interfere with the standardization process (they are going to great lengths to separate themselves from it now. . . . " (R 593 at 2). 461. Although the IEEE later issued the proposed RamLink standard, no product implementing the RamLink standard ever came to market. (prince, Tr. 9012). Hyundai Negotiates "Other DRAM" Provision As Part of Its RDRA License Agreement 462. Afer Hyundai became aware that Rambus might have patents covering aspects of SyncLink, it negotiated an "Other DRA provision in its license agreement with Rambus as a kind of "insurance program." A draft amendment to the license agreement was sent by Rambus to Hyundai and expressly listed SDRA and DDR SDRA as examples of "Other DRA under the agreement. (RX 2275 at 1). This "Other DRA provision permtted Hyundai to use Rambus technology in DRAs other than RDRAs, on the condition that Hyundai complied with its contractual obligations, including an itemization of all products subject to royalties, the marking of all such products with Rambus proprietary markings, providing royalty reports showing shipments of all such products each quarter, and ongoing payments of royalties for such products. (CX 1599 at 12- , ,-,- 5. , 5. 5). 463. Hyundai and Rambus signed a license agreement in December 1995. Included in the Hyundai-Rambus license agreement is an "Other DRA provision that granted Hyundai the right to use Rambus technology in DRAs other than RDRAs, subject to payment of a 2. royalty. (CX 1599 at 3 , 12; Crisp, Tr. 3320-22; see also CX 2107 at 84- , 91-92 (Oh Dep. )). The SyncLink Consortium Formation and Purpose of the Consortium 464. In August 1995 , Hyundai, Mitsubishi, Mosaid, Texas Instruments, Micron Samsung, and Apple formed the SyncLink Consortium. (R 591 at 1; RX 610 at 1). Companies joining later or sending attendees included Hitachi, Fujitsu, NEC, Hewlett-Packard, ffM Panasonic, Molex, VIS, AM, and Vanguard International. (RX 2090 at 7-8). Members included not only DRA suppliers, but also customers and other companies. (Tabrizi, Tr. 9177- 78). Of the thirty-four companies that attended at least one SyncLinkSLDRA Inc. meeting in 1996 or 1997, thirty-one also attended a JEDEC 42. 3 meeting in that same time period. (Respondent' s Submission Regarding Company Attendance at SyncLink and JEDEC 42. Meetings (October 28, 2003)). 465. The SyncLink Consortium,was intending to develop the next generation main memory architecture that could be used in various applications, including personal computers servers, workstations and various other segments of the market. (Tabrizi, Tr. 9126-27; see also RX 591 at 2). 466. While the SyncLink Consortium represented to the public that it was "developing an open, royalty-free industry standard " the Consortium members had agreed among themselves that the SyncLink-related patents would only be freely available to members of the Consortium and its corporate successors, SLDRA Inc. and Advanced Memory, Inc. ("AM2" ). (Compare RX 765 at 1 (9/9/96 press release referencing a "royalty-free standard" ), with RX 591 at 2 (8/22/95 SyncLink minutes stating that patents wil be "freely available to Consortium members )) . 467. The SyncLink Consortium received a patent on the SyncLink pinout itself - the very specification that had been standardized by JEDEC. (Rhoden, Tr. 1211; see RX 2086). 468. Moreover, AM2 Chairman and JEDEC President Desi Rhoden, who is a named inventor on the SyncLink "pinout patent " testified that when SyncLink announced that SLDRA would be "royalty free " that did not mean free. (Roden, Tr. 1214). 469. In fact, the Consortium s corporate successor has offered to license the patents at reasonable royalty rates. (R 1858 at 1). 470. The SyncLink Consortium was formed as a consortium outside ofthe IEEE in par because the Consortium members did not consider the IEEE rules regarding disclosure of patents to be satisfactory. Because individual members in the IEEE represented only themselves and not any company, there was no obligation of patent disclosure. (Tabrizi, Tr. 9120, 9122). 471. The SyncLink Consortium members shared know-how and design experience relating to the SyncLink architecture. (Tabrizi, Tr. 9128-29). 472. The SyncLink Consortium members also shared the cost of development of the first chip and the expenses associated with other projects. SLDRA Inc. levied special assessments of its members as needed for different projects. (Tabrizi, Tr. 9128). Concern About Patents of Non-Members 473. The SyncLink Consortium applied for and held patents in its own name. (Tabrizi 9124-25; Gustavson, Tr. 9314). 474. Consortium members used the patents to encourage companies to join the Consortium (and its successor, AM2) and to discourage members from resigning from the Consortium. (See RX 1100 at 2; RX 1362 at (in camera)). 475. Members of the SyncLink Consortium were particularly concerned about avoiding Rambus s patents. (CX 488 at 2; see also Gustavson, Tr. 9302-03). SyncLink' s Activities With Respect to Rambus Patent Applications and Intel' s Announced Support of RDRAM 476. As previously noted, the SyncLink Consortium Secretary, Dr. David Gustavson reviewed Rambus s pending European patent applications along with two other Consortium representatives and determined that the SyncLink device would infinge if the applications ever issued as patents. (Gustavson, Tr. 9286-87). Gustavson did not, however, believe that the patents would issue, (Gustavson, Tr. 9286-87), and Hans Wiggers, the chair of the Ramlink Commttee, believed that Rambus was simply trying to "torpedo" the Ramlink and SyncLink standards. (Wiggers, Tr. 10589). 477. Similarly, in April 1997, Micron JEDEC representatives and JEDEC Council member Terry Walther thought "that is old technology." (R 920 at 1). Another Micron JEDEC representative, Terry Lee, testified that when he learned that Rambus planned "to request royalties on all DDR memory efforts" (R 920 at 2) in April 1997, he "didn t believe this was true " and he did nothing to follow up. (Lee, Tr. 6981). 478. Certain JEDEC members, especially the leadership of the 42.3 commttee, held views that the Patent Offce often issued patents for "old technology," as Walther put it, and the 42. 3 commttee even considered offering its services as "a source of expert opinions on memories to the patent offce." (JX 32 at 2). JEDEC 42. 3 members therefore, might well have believed that any Rambus patents on features as on-chip PLL or dual edge clocking would be invalid because of prior art. (See, e. CX 711 at 37). 479. In late 1996, Intel announced that its future chipsets for main system memory in personal computers would support exclusively Rambus s RDRA. (Tabrizi, Tr. 9134-35). As a result ofthat decision, DRA manufacturers expected SyncLink to be relegated to nonapplications, including servers, Apple-based computers, and systems using UNX-based processors. (Tabrizi, Tr. 9134- , 9137). 480. Following Intel' s announcement of its decision to support only RDRAs for main memory in future PC systems, Tabrizi organized a meeting of executives representing the SyncLink Consortium members in January 1997 to determne the future of the SyncLink Consortium. (Tabrizi, Tr. 9138-39; RX 808 at 1-2). 481. At the meeting, the level of support for the SyncLink Consortium varied from company to company; the participants agreed to continue at least to support the SyncLink Consortium s development work, but not to commt major resources to ii. (Tabrizi, Tr. 9139- 40). 482. Because Intel supported Rambus, Hyundai executive, Dr. Oh believed he had no choice but to produce RDRA. (CX 2107 at 117 (Oh, Dep. )). In order to produce RDRAs, Dr. Oh believed that Hyundai needed to have support from Rambus. (CX 2107 at 118- 19 (Oh, Dep. )). 483. Dr. Oh thereafer instructed Tabrizi to resign from the competing SyncLink Consortium. (CX 2107 at 117 (Oh, Dep. )). 484. By the fall of 1998, Intel informed Tabrizi that "they would like to start working on Intel next generation memory solution beyond RDRA as soon as possible " and that they wanted to develop that post-Rambus device with the DRA manufacturers instead of continuing to develop further generations of Ram bus memory. (R 1361 at 1). 485. In a December 1998 email to Dr. Oh, Tabrizi said: "I am no longer head of SLDRA Inc. as of 12/17/98, and I believe the organization wil die slowly from here on. Job accomplished." (R 1361 at 1). 486. The SyncLink architecture was not accepted within the industry and never went into volume production. (Appleton, Tr. 6319; Tabrizi, Tr. 9184; Peisl, Tr. 4492). An ffM engineer had pointed out as early as 1996, the SyncLink device appeared to be "vaporware compared to Rambus. " (RX 839 at 1). Rambus s Relationships With Intel and DRAM Manufacturers Rambus Sought Licenses and Support for RDRAM From DRAM Manufacturers After Intel Endorsed RDRAM Technology 487. In late 1995, Intel made an internal decision that it would support the proprietary Rambus RDRA technology with the next generation ofIntel microprocessors. (R 1532 at 1). The decision was followed by a lengthy period of meetings and negotiations with Rambus and with DRA manufacturers. (RX 1532 at 1-2). 488. Intel and Rambus signed a contract in November 1996 and Intel announced that its future desktop PC chipsets would only work with RDRA. (R 1532 at 2; Tabrizi, Tr. 9135; Crisp, Tr. 3432-33; CX 2634 at 1). During this time, Intel controlled about eighty percent of the . market for microprocessors used in personal computers. (Tabrizi, Tr. 9138-39). 489. During the beginnng of the Rambus-Intel partnership, Intel hoped that Rambus would be a "value-added part of this whole industry infastructure." (MacWillams, Tr. 4870-71). Intel envisioned an industry infastructure where DRA vendors built DRAs, Intel built chipsets, and "Rambus provide ( d) all ofthe glue to make the enabling pieces work and therefore would be perceived as valuable." (MacWillams, Tr. 4871). 490. Projected demand for RDRA increased sharply after Intel announced it would produce chipsets that used RDRA. (Hampel, Tr. 8677-78). 491. According to an April 21 , 1996 Microprocessor Report article: "Intel's move was motivated by the incessant need to provide more system-level performance" and "Rambus had a proven track record of delivering cheap, high-bandwidth systems. " (CX 2634 at 1). 492. In the Microprocessor Report article, Rambus s royalties were noted as being: an emotional issue for many in the DRA industry, yet these royalty relationships are commonplace in the DRA industry. Texas Instruments for example, currently derives more income from its DRA patent portfolio than Rambus can reasonably expect to generate within the next decade. The aggravating issue is not so much royalties per se but new and blatantly aboveboard royalties. Also, because Rambus is an intellectualproperty company, its licensing relationships do not have the same sense of reciprocity and quid pro quo as do other licensing arrangements in the industry. (CX 2634 at 3). 493. Micron Chairman Steve Appleton was surprised about Intel' s decision to endorse Rambus. (Appleton, Tr. 6344). 494. Afer Intel' s support ofRDRA, Micron engaged in licensing negotiations with Rambus because "the probabilities of customers in the marketplace actually using it increased quite a bit, and as a result, we also then believed that some customers would use RDRA and that we needed to then engage to negotiate for a license." (Appleton, Tr. 6345-46). 495. t ) (CX 2699 at (in camera)). 496. In February 1997, Mitsubishi signed a license agreement with Rambus covering Direct RDRA. (CX 1609 at 1- 19). The subject matter of the Mitsubishi agreement was limited to Rambus-compatible DRAs, interfaces and matters such as design and development support. (CX 1609 at 1-2). 497. In March 1997, Hyundai amended its RDRA license agreement with Rambus to include Direct RDRA. (CX 1612 at 1-7; CX 1599 at 1-23; CX 1600 at 1-22). Hyundai' s new agreement included royalties on Direct RDRA ranging from 1.5% to 2. 0% depending on the sale date and the relative revenue for the sales. (CX 1612 at 5). 498. In March 1997, Micron signed a license agreement with Rambus covering Direct RDRA. (CX 1646 at 1-20). Micron agreed to pay a royalty rate up to 2% on next generation RDRA and included a provision to buy down the royalty rate. (CX 1646 at 11). 499. Micron decided to sign a license agreement for Direct RDRA because "(w)e felt that with Intel' s endorsement, that there would be a customer base that would use the product and we needed to be in a position to make whatever product that the customer decided that they were going to use for their platforms." (Appleton, Tr. 6346-47). 500. In July 1997, Siemens signed a license agreement with Rambus covering RDRA. (CX 1617 at 1-22; CX 2088 at 62 (Tate, Infneon Trial Tr.)). Intel and RDRAM Royalty Rates 501. Intel wanted to keep the cost ofRDRA low so that DRA vendors would be motivated to build RDRA. (MacWilaims, Tr. 4849-50). 502. Intel' s contract with Rambus capped the royalty rate that Rambus could charge for RDRA technology at two percent. (CX 2634 at 3-4). 503. Intel sought to persuade Rambus to keep its royalty rates low throughout the 1996- 1998 time frame. (CX 936 at 1; CX 912 at 2; CX 952 at 2; Farmwald, Tr. 8404). 504. In September 1997, Rambus CEO Geoffey Tate and Rambus Vice President David Mooring met with Intel executives Gerr Parker and Pat Gelsinger. (CX 952 at 1). Intel requested that Rambus, among other things, lower its RDRA royalties even further to help overcome DRA maker resistance to producing RDRA devices. (CX 952 at 2). Intel explained that ifRambus did not lower its RDRA royalties, this could cause DRA makers " find alternate solutions to avoid paying rambus a royalty" and could cause Intel to "rearchitect things to be completely different if necessary." (CX 952 at 2). 505. In October 1997, Rambus CEO Geoffrey Tate had a meeting with Pat Gelsinger, the senior Intel executive responsible for the Rambus relationship. The purpose of the meeting was to follow up on Gelsinger s earlier request that Rambus "lower our rdram royalties to -:0. " and his suggestion that ifRambus failed to do so DRA makers would insist on developing alternatives to RDRA. (CX 961 at 1). 506. The October 1997 Rambus-Intel meeting focused in part on the extent to which DDR had "GAID ground" with PC manufacturers and thus was a "threat" to RDRA. (CX 961 at 2-3). Intel believed that at least one DRA maker was promoting DDR because of Rambus s royalty rates on RDRA. (CX 961 at 5). 507. Intel did not believe that there was a problem with Rambus s business model other than the fact that many ofthe DRA manufacturers disliked it. (CX 1016 at 3-4). Design, Manufacture, and Supply of Memory Architectures by Micron and Other DRAM Manufacturers 508. From approximately 1996- 1999, some companies, such as Micron and Hynix felt the DRA industry was developing different memory architectures for different market segments. Companies planned to use RDRA as main memory in mid-range and high end personal computers; DDR as main memory in servers and for graphic applications; and SyncLink as the possible next generation main memory in PCs. (CX 2718 at 45; Lee, Tr. 6727-28; CX 2297 at 3 81). 509. Hyundai made commtments to deliver RDRA to customers based on customer needs. (CX 2303 at 7; Tabrizi, Tr. 9164-66). However, in 1998, Hyundai' RDRA production commtments were not met. (Gross, Tr. 2327-29). 510. Compaq planned to transition to RDRA because ofIntel' s roadmap and planned to introduce RDRA throughout its product line. (Gross, Tr. 2318 2326-27). 511. Micron s CEO Steve Appleton, testified that Micron devoted many resources to developing RDRA after Micron signed a license for Direct RDRA in 1997. (Appleton Tr. 6354-57). He stated that Micron formed a large design team to work on RDRA and offered the team cash incentives to meet certain milestones. (Appleton, Tr. 6355-56). 512. In October 1998, however, Micron proposed to other DRA manufacturers that they agree to a "common roadmap" that the manufacturers would then provide to chip set companies and PC original equipment manufacturers ("OEMs ). (R 2191 at 1; RX 2192 at 3; Soderman, Tr. 9354). The "main target" of such a joint roadmap would be to remove the current uncertainty about the supply situation" among the chipset companies and PC OEMs. (R 2191 at 1). A proposed joint market forecast was later circulated to numerous DRA manufacturers by Micron. (R 1423 at 1-2). 513. In an April 1999 email exchange among Micron Vice President Bob Donnelly, Micron DRA Marketing Manager Jeff Mailoux, and Micron JEDEC representatives Kevin Ryan and Terry Lee, an article was attached describing Samsung s plans to produce as much as forty millon Rambus devices in 1999. (R 1444 at 3). In response, Ryan complained that Samsung had "broken ranks with the other suppliers and sold their soul to the devil." (R 1444 at 1). One of the recipients of the email, Mike Seibert, responded that "(tJhese guys (Rambus) are big trouble for us all. Ifthis thing gets into an oversupply mode with RDRA things could get really ugly. " (RX 1444 at 1). Seibert then asked Micron Vice-President Bob Donnelly if Samsung understood "what the Rambus/Intel biz model wil do to our autonomy?" (RX 1444 at 1). Vice-President Donnelly responded that he had "certainly made the point with the offcers that Intel. . . ultimately could control the DRA industry." (R 1444 at 1). 514. In April 1999, Micron completed its higher 144Mb Rambus design and taped out the part, meaning Micron sent it off for fabrication. (CX 2735 at 24 29; Lee, Tr. 6744-45). Micron indicated that it expected to release its 144Mb samples in June 1999. (CX 2735 at 31). However, according to an Intel analysis of Micron RDRA performance as of May 1999 (t)echncally, they are well behind. " (RX 1453 at 1). As a result, Intel felt, Micron was only marginally able to ship anything at all in ' 99." (R 1453 at 1). 515. Intel concluded in May of 1999 that Micron s plan was intended to "create as much turmoil to prevent rdram as possible." (RX 1453 at 1). The Intel analysis stated: Marketing - they (Micron) are aggressively rallying the industry on alternate technologies. They are clearly driving the Sdram- 133 alternatives, they are strongly driving ddr and the only player left driving sync-link. Their advertising implies that the rest of the industry is blindly following the Intel roadmap (sheep, communism etc). Should make you mad.. . Relationship - we ve tried to broker a deal with rambus (fixing contract in area of ip pooling, royalties and marketing) and per earlier mails, with their - advertising and aggressive drive to alternatives, they pissed rambus off enough that any hope of an agreement is pretty dead. They have also ignored our attempts to work with them on enabling, design reviews roadmap alignment etc. (RX 1453 at 1). 516. By October 1999, an Intel manager explained to Intel's Peter MacWiliams , " (s)o far all our discussions with Appleton have had zero benefit for us. . .. (w)e have gone out of our way to help them resolve Rambus contract issues and in return we have gotten nothing but deception. Micron is working very hard to do everyhing against RDRA." (RX 1515 at 2). Cost Issues Associated With RDRAM 517. In the 1998 time frame, DRA manufacturers estimated that RDRA would be more costly to produce than other DRAs. (Gross, Tr. 2364-66). This impression had come from DRA suppliers and Intel. (Gross, Tr. 2367-68). 518. Hyandai executive Tabrizi admitted at trial that in October 1998 , Hyundai gave RDRA production forecasts to Intel that were deliberately infated. "Intel was not happy with our ramp up, so we gave them a very optimistic number on our side. (Tabrizi, Tr. 9092; see also RX 1295 at 1 (internal Hyundai email, copied to Tabrizi, that states that, from the perspective of the Hyundai America marketing group, "we can overstate our Direct Rambus production so Intel can feel we are more aggressive on the ramp up. )). 519. In a February 2000 email asking Micron to supply it with RDRA, Dell similarly stated that it was "commtted to Rambus" but that its ability to incorporate Rambus devices in its PCs was "clearly limited by supply." (RX 1560 at 1). Looking ahead to the second half of2000 Dell projected that with lower pricing, up to forty percent of its market demand would be satisfied with RDRA technology. (RX 1560 at 1). 520. Several factors might have contributed to the high cost of producing RDRA including "the packaging, handlers, burn-in equipment, die size, licensing, and test. Some of these areas wil require the purchase of new manufacturing equipment, and some areas have an inherently higher manufacturing cost." (CX 2716 at 1; CX 2083 at 132-33). However, this does not explain why DDR SDRA prevailed in the marketplace in lieu ofRDRA, for all of these issues were present in connection with the product introduction of the DDR device, as Micron CEO Appleton confirmed in an analyst call in September 2002. (See RX 2067 at 7). 521. As Craig Hampel, Techncal Director of Ram bus explained, test cost analyses that focus on capital expenditures depend in large part on the volume of devices tested. Assuming equivalent volume production ofthe RDRA and SDRA devices, test costs would be at least equivalent, and because of the high speeds at which the Rambus device could be tested, could even be less for the RDRA devices. (Hampel, Tr. 8703-04). 522. Dell understood that the RDRA cost premium inhbited the development and production ofRDRA. (CX 2180 at 1 4). 523. As Compaq executive Gross testified, and as Compaq s documents show, OEMs were facing a shortage ofRDRA created because the "suppliers have not invested to support current Rambus demand for 1999." (RX 1287 at 4; Gross, Tr. 2346). 524. Intel had concerns about the cost ofRDRA. (CX 974 at 1). In or around 1998 Intel had concerns regarding whether the cost of manufacturing RDRA would ever be comparable to the cost of making SDRA because the price of SDRA had dropped significantly. (CX 2541 at 1; CX 2887 at 1; RX 1532 at 2). 525. Elpida Memory, Inc. ("Elpida ) expected lower projected RDRA costs than DDR costs in 2002 and 2003. (RX 1762 at 42). The same Elpida presentation described RDRA the most competitive leading process available. (RX 1762 at 43). Actions by DRAM Manufacturers 526. In September 1996, Hyundai executive and SyncLink Consortium chairman Farhad Tabrizi wrote an email that expressed a concern that "the real motive ofIntel is to control DRA manufacturers. . . ." (R 778 at 1). According to Tabrizi, Intel' s actions would give it "control of DRAs and other CPU makers. We wil become a foundry for all Intel activities and (i)fIntel would like and desires to do business with us then we may get a small share of the their total demand. " (RX 778 at 1). Tabrizi concluded his email stating: "I urge you to please educate others and get their agreement to say 'NO TO RAUS AN NO TO INTEL DOMIATION. '" (R 778 at 1). 527. Tabrizi sent this email to Jim Sogas at Hitachi, for comments. (R 778 at 1; Tabrizi, Tr. 9035, 9037-38). 528. In December 1996, at a SyncLink Consortium meeting attended by various manufacturers, Tabrizi stated that " (m)any suppliers are paranoid over the prospect of a single customer, e. , Intel, having control of market. We can t resist such a possibility individually. We need some united strategy. " (RX 808 at 2). 529. At that same meeting, the assembled manufacturers agreed to hold a meeting of DRA manufacturer executives in Japan in January 1997. (Tabrizi, Tr. 9041). Prior to the meeting, Tabrizi sent an email to other DRA manufacturers that stated that the "Intel decision to go on a Rambus route was pure political and domination and control over the DRA suppliers and not techncal." (R 802 at 3; Tabrizi, Tr. 9041-42). He then stated: "As I have mentioned many times before, Intel does not make DRAs, we do. And if all of us put our resources together, we do not have to go on this undesirable path. The path of control and domination by Intel." (R 802 at 3). He urged the DRA manufacturers to "stick together on this matter. (R 802 at 3; Tabrizi, Tr. 9042-43). 530. Tabrizi' s January 1997 presentation also stated that ifRambus became the next generation memory solution , " ALL DRA COMPANS WIL BECOME FOUNRIS for a single source CPU manufacturer." (R 849 at 44). The phrase "single source CPU manufacturer" was a reference to Intel. (Tabrizi, Tr. 9046). 531. Micron engineer Terry Lee participated in the January 1997 DRA executive meeting; his notes reflect that Siemens stated that " (c)ontrol concerns are realistic. " (CX 2250 2; Tabrizi, Tr. 9047-48). Lee s notes were later made available to all members of the SyncLink Consortium (which was renamed the "SLDRA Consortium" around this time). (Tabrizi Tr. 9050; RX 855 at 1). 532. Afer the January 1997 DRA executive meeting, Tabrizi set up an email reflector" so that the DRA supplier executives could communicate with each other. (Tabrizi Tr. 9052-53; RX 938 at 1). 533. In February 1998, Jeff Mailoux of Micron wrote an email to Tabrizi stating that Mailloux had spoken to a reporter for an industry publication called EE Times. (RX 1105 at 1). Mailloux stated that "I told him that at any density, and any process that is available in 1999 RDRA is at least 30% cost adder for Micron " and then encouraged Tabrizi to call the reporter with Hyundai' s views. (RX 1105 at 1). 534. Two months later, Mailoux sent another email to Tabrizi, attaching an article in an industry publication that had been written by Tabrizi' s boss at Hyundai, Mark Ellsberry. (R 1155 at 1; Tabrizi, Tr. 9055- 56). His email states , " Mark seems to give a message at the end here, he only refers to DDR as a ' long shot' and does not even mention SLDRA. Hope Hyundai has not caved in to the ' dark side. '" (RX 1155 at 1). 535. In April 1998, Bert McComas, an industry consultant, gave an exclusive seminar for DRA manufacturers about Intel's selection ofRDRA. (R 1138 at 1; Tabrizi, Tr. 9061-62). McComas pre-cleared his seminar invitation and list of topics with Tabrizi. (Tabrizi, Tr. 9064). 536. McComas s invitation asked its recipients not to forward the invitation to Rambus or Intel. (R 1138 at 1). 537. During his April 1998 seminar presentation to the DRA manufacturers, McComas stated that a manufacturer that chose to build RDRAs was making a "guaranteed bad bet for margin enhancement " and he stated that RDRA deepens the manufacturer s financial dilemma. (RX 1482 at 12 26). As a "possible strateg(y)," McComas suggested that DRA manufacturers (t)ape out but do not fully productize or cost reduce" the RDRA device, in an effort to "resist popular deployment" ofRDRA. (R 1482 at 34-35). 538. Afer the seminar, McComas accepted an invitation to speak at the next SLDRA Consortium Executive Meeting, so-called because company executives attend in addition to engineers and marketing personnel. (Tabrizi, Tr. 9066-68). In an April 17, 1998 email extending the invitation, Roberto Cartell of Texas Instruments wrote to McComas , " I personally believe that your story on Intel and its relationship to Rambus, is an excellent ' case for action' story to stimulate discussion among industry executives." (RX 1166 at 1; Tabrizi, Tr. 9068). 539. McComas spoke at the June 25 , 1998 SLDRA Executive Summt about the problems faced by DRA manufacturers. One ofthe tactical issues he identified was how to Manage Price Competition, Profitability." (RX 1188 at 1). He also talked about how manufacturers could "Respond to the Strategic Threat of Intellambus " and he asked the question , " Who wil control the DRA industry?" (RX 1188 at 1). McComas stated that Intellambus are using your money to take control ofthe DRA industry" and that Intel would ( 0 Jrchestrate early oversupply situation " and he emphasized that "(fJragmented competition undermnes all DRA manufacturers." (R 1188 at 2 6; Tabrizi, Tr. 9073). 540. Another industry consultant, Victor de Dios, also gave a presentation at the June 25 1998 SLDRA Executive Summt. (Tabrizi, Tr. 9071-72). De Dios told the assembled executives that "many of the problems are industry problems, not company problems. Competition wil not resolve them." (RX 1204 at 4 (capitalization omitted)). 541. During his presentation at the June 1998 "Executive Summt " McComas suggested that the DRA manufacturers share theirRDRA production plans to determine whether there would be a demand-supply imbalance. (Tabrizi, Tr. 9073-74). 542. In an August 1998 email to Tabrizi, McComas sent a draft message to DRA manufacturers which stated that " (d)uring the critical production ramp-up phase of Direct Rambus, DRA vendors will need a constant flow of information to help make wise decisions and to walk the fine line between a pleasant shortage and a disastrous over-supply." (R 1232 at 1). 543. Tabrizi agreed that a shortage ofRDRA would please DRA manufacturers because "(p)rices go up. " (Tabrizi, Tr. 9077). 544. The PC OEMs recognized that for RDRA to succeed, output ofRDRA had to increase. They tried to infuence the DRA manufacturers to increase RDRA output. (R 1287 at 4 ("Intel and major users have been trying to infuence improve (sic) RDRA output")). As Gross of Compaq testified, Intel, Compaq, and other PC OEMs were trying to infuence DRA manufacturers to increase output ofRDRA and to align roadmaps with Intel' roadmap. These OEMs wanted an RDRA production ramp-up so that they would have suffcient availability and lower RDRA prices. (Gross, Tr. 2318-20). 545. It was important to Intel and to the PC OEMs that the DRA vendors increase the volume ofRDRA because the highest volume parts have a cost advantage. (RX 1532 at 1). 546. In response, DRA manufacturers agreed to manufacture RDRA in larger volume. For example, in 1998, Hyundai committed to produce 30 000 RDRA units for Compaq. (R 1302 at 6). Similarly, Micron commtted to produce 15 000 RDRA units for Compaq. (RX 1302 at 6). Neither company, however, met these commtments. (Gross Tr. 2327-29). According to Compaq, the DRA manufacturers would not "increase their output at the rate at which we needed to support our systems. " (Gross, Tr. 2345-46). 547. Tabrizi, in 1998, believed that Intel would not change course unless RDRA failed to obtain market penetration. (Tabrizi, Tr. 9082-83). He admitted that one way to cause RDRA to fail to obtain market acceptance was if the OEMs were convinced that even if volumes went up, prices would not fall. (Tabrizi, Tr. 9083). If the OEMs were convinced of this they would not adopt RDRA. (Tabrizi, Tr. 9083). 548. In the fall of 1998, Hyundai gave RDRA price projections to its customers that were significantly higher than those reflected in its internal pricing documents. (Tabrizi, Tr. 9085- 90; RX 1280; RX 1293A). "Intel was tellng everybody (that RDRA is) only going to be a 5 percent premium. . . . I wanted to make sure my OEM knows it's going to cost them more than 5 percent. . . " (Tabrizi, Tr. 9091-92). 549. A report prepared by an Infneon engineer about an October 1998 meeting reportedly attended by Tabrizi, along with engineers from Micron and Infneon, states that (a)ccording to Farhad Tabrizi, Hyundai has given Rambus ASP projections for end of next year of2 to 3 times of to days SDRA prices; they also gave to Intel a production projection of three times their actual plans =)- They encourage every DRA manufacturer to do the same in order to let Intel not generate a Rambus oversupply." (R 2192 at 2). Tabrizi denied at trial that he had made the statements attributed to him in the Infneon trip report. (Tabrizi, Tr. 9097). 550. In January 1999, Desi Rhoden sent a proposal to all of the major DRA manufacturers regarding the transformation of the former SyncLink Consortium (by then called SLDRA Inc. ) into a marketing-oriented organization called Advanced Memory Inc. AM2"). (RX 1373 at 1-3). Rhoden became the President and Chief Executive Offcer AM2. (Roden, Tr. 260, 696- , 1235). Rhoden stated that the focus of the new organization would be to "co-ordinate instead of developing new technology." (R 1373 at 3). He also stated that " (i)n the DRA industry, we are clearly stronger together than we are individually. (R 1373 at 1). 551. In a July 1999 email, Mario Martinez ofHyundai recommended to Tabrizi and others at Hyundai that "( w )ith Samsung building significant amounts of product, we need to work with them to limit the supply in the market, otherwise we both will be competing for market share which wil result in an oversupply. We have to meet with Samsung and discuss our and their production plan, TAM analysis and targeted market share." (R 1487 at 4; Tabrizi, Tr. 9103). 552. Another Hyundai employee responded in the same email: "(I) have connection in samsung, ifi know, what time you are available, i wil try setup meeting with key persion (sic) in samsung in seoul korea. (A)nd i will try persuade them. (A)ctually they also have same idea for rambus business compare with you." (R 1487 at 4; Tabrizi, Tr. 9104). 553. Tabrizi admitted at trial that he had told Sang Park, then the President and Chief Operating Offcer ofHyundai, that he wanted to "kill" Rambus and force RDRA from the market. (Tabrizi, Tr. 9105-07). Tabrizi subsequently testified that what he meant by "killing Rambus was really just "Rambus suicide, (with) me watching on the sideline. " (Tabrizi Tr. 9109). In his June 2000 email to Park, Tabrizi stated: " (i)fIntel does not invest in us, I really want to ask you to let me go back to myoid mode ofRDRA killng. I think we were very close to achieving our goal until you said we are absolutely commtted to this baby." (R 1661 at 2). 554. Gross of Compaq subsequently testified that because the price ofRDRA did not decrease and because Compaq did not believe that it would decrease in the future, Compaq decided to abandon its plans and to shift to DDR. (Gross, Tr. 2339). 555. Similarly, Advanced Micro Devices ("AM") shelved plans to adopt RDRA because, based on what they were told by DRA manufacturers, it was clear that DDR, not RDRA would become a commodity product. (polzin, Tr. 4013). 556. By May 2000, the situation had not improved, and Dell was considering moving into a low key Rambus mode." (R 1636 at 1). The Dell "message" was "pretty straightforward" Dell has booked our products over the last year around the assumption that RDRA prices would decline and close on SDRA. This would help us create demand. ..... The memory vendors have shown no desire to drop prices, therefore we are reevaluating our strategies...... so the message to them is drop prices or we wil continue to decrease our RDRA forecasts and we wil architect next generation systems around DDR ..... we wil give the memory vendors til the end of May to reply to our request ..... if they stil have no desire to drop prices, we should push ahead rearchitecting chipsets around DDR. (RX 1636 at 1). 557. RDRA failed to command significant market share despite the fact that it was considered by some to be the "best solution." (R 1762 at 5). As Peter MacWiliams ofIntel put it: (MacWillams, Tr. 5075 (in camera)). 558. Subsequently, in a November 26 2001 email aMicron manager named Kathy Radford described the efforts ofInfneon and Samsung to raise DDR prices, and stated that Micron intended to try to raise its prices to all of the OEM customers. (R 1922A at 1). Radford then reported that "(tJhe consensus from all suppliers is that if Micron makes the move all of them will do the same and make it stick." (R 1922A at 1). 559. Prices did, in fact, increase in the months after Radford' semail. On March 1 2002 J (RX 1991 at 1 (in camera)). The DRAM Industry s Approach to Addressing RDRAM Problems 560. Intel and Rambus executives discussed ways to fix Rambus s relationship with the DRA manufacturers. (MacWiliams, Tr. 4871-72). Rambus "seemed to be sensitive to the fact that they needed to fix" problems with DRA manufacturers. (MacWiliams, Tr. 4873). 561. In 1998; Intel continued its work to make RDRA a market success by investing in DRA companies that developed and supplied RDRA. (CX 1006 at 1; CX 2522 at 2-3). 562. Intel did not succeed in mending the relationship between Rambus and the DRA manufacturers. (MacWillams, Tr. 4874). By 1998 the Rambus-Intel Relationship Was Deteriorating 563. On April 14, 1998, Rambus CEO Geoffey Tate and Chairman Wiliam Davidow met with Pat Gelsinger ofIntel to discuss Intel's concerns about Rambus. (Farmwald, Tr. 8402; CX 1016 at 1; CX 2109 at 175-76 (Davidow, Dep. )). The basic message of the meeting was that in the intermediate term Intel would continue to support RDRA, but Intel might support a competing architecture for the next generation. (CX 1016 at 1-4). 564. Afer the April 14, 1998 Rambus-Intel meeting, Tate began strategizing about how to address Intel' s announcement that it would compete with Rambus. (CX 1016 at 1-4). 565. On April 15, 1998, Farmwald responded to Tate s concerns about Intel's commtment to RDRA emailing: "I'm not even sure we want to agree to work together on the next generation memory interface." (Farmwald, Tr. 8406-07; CX 1021 at 1). 566. On April 16, 1998, Rambus Chairman Willam Davidow responded to Farmwald' email by urging a more measured approach. (Farmwald Tr. 8407; CX 1022 at 1). Davidow suggested that Rambus "try to negotiate something" with Intel. (CX 1022 at 2). Technical Problems and Product Delays With RDRAM 567. During this period, the Camino Chipset, also called the Intel 820 Chipset , " was the first chipset that Intel was developing to interface between their processor and direct Rambus. (MacWilaims, Tr. 4853; Tabrizi, Tr. 9166, 9185). The Camino Chip set was intended to interface exclusively with RDRA. (Tabrizi, Tr. 9185-86). 568. In the second half of 1998, Intel encountered electrical issues with RDRA. (R 1532 at 2; MacWillams, Tr. 4852-53). Techncal problems with RDRA forced Intel to delay the Camino Chipset launch several times. (MacWiliams, Tr. 4852-53; Tabrizi, Tr. 9185). 569. Similarly, the design and ramp up phases ofDDR SDRA' s launch experienced delays and diffculties. (Reczek, Tr. 4349-51 (transition to DDR was a major change, and Infneon had to implement three major redesigns before it could achieve acceptable performance); Shirley, Tr. 4208-09 (f (in camera)). 570. In April 1999, Intel' s microprocessor rival, AM, suspended development work on its RDRA product due to continuing bad news about RDRA. (CX 2158 at 1-2). Steven Polzin, of AM, testified that the information regarding RDRA costs and yields came from what he was hearing from the memory manufacturers. (Polzin, Tr. 4013). In late summer or fall of 1998, AM shifted its focus to DDR because AM believed Rambus was going to fail as a commodity part, and that ultimately even Intel would have to go DDR. (Heye, Tr. 3704- 3799). 571. In May 1999, Intel' s customers were skeptical that the cost and availability issues with RDRA could be resolved although some were waiting to see progress. (CX 2529 at 1; MacWillams, Tr. 4884)). 572. In May 1999, Intel considered adding DDR SDRA to Intel's server memory roadmap because it was concerned that RDRA would not achieve the cost points in time to be competitive for the server products. (MacWiliams, Tr. 4883-84; CX 2529 at 1). Intel' s Announcement That It Would No Longer Support RDRAM 573. By mid-October 1999, Intel's road map included SDRA and DDR SDRA solutions as well as RDRA. (CX 2540 at 1). 574. In late October 1999, Intel told Rambus that it wanted to have a comprehensive review of their business relationship. (CX 2887 at 1). 575. Intel announced in its October 26, 1999 letter to Rambus that its chipset roadmap now included alternatives to RDRA. (CX 2541 at 2; CX 2887 at 2-3). 576. In June 1999, Intel publicly ceased its exclusive support ofRDRA and announced that the Pentium III chipset would support SDRA. (Tabrizi, Tr. 9201-03; CX 2338 at 57 (in camera)). 577. This was the first time Intel indicated that SDRA could compete with RDRA the interface with Pentium III. (Tabrizi, Tr. 9201-03). 578. In August 1999, Intel confrmed that it would provide support for SDRA in the Pentium III chip set. (Tabrizi, Tr. 9201-03). 579. Afer Intel announced its support of SDRA, Rambus s percentage of market penetration dropped because customers could choose between SDRA and Rambus technologies. (CX 2338 at 57 (in camera); Tabrizi, Tr. 9203-08). 580. During 1999 and 2000, Intel revised downward its estimates for the total available market for RDRA multiple times. (CX 2338 at 79 (in camera)). 581. Intel reduced its estimates for the total available market for RDRA the second and third quarters of2000. (CX 2338 at 79 (in camera); Tabrizi, Tr. 9193-97). 582. Micron never introduced RDRA into the market for commercial sale. (Appleton Tr. 6371-74). 583. On September 2001 , Micron Vice-President Sadler f (RX 1883 at (in camera)). 584. As projections for RDRA declined in the 1999-2000 time frame, the anticipated market share shifted to SDRA and DDR SDRA. (Tabrizi, Tr. 9214- 15). 585. Samsung, the world' s largest DRA producer, began commercialization and full production ofRDRA. (Appleton, Tr. 6373). 586. In February 2001 , nearly a year and halflater, Intel was stil announcing that its memory strategy was to shift from SDRA to RDRA for desktop space. (R 1762 at 4). According to Intel' s presentation at the Intel Developer Forum, Spring 2001 , RDRA was the best solution, the best technology for the Intel Pentium 4 Processor Platform, and "RDRA Remains the Primary Desktop Memory Solution." (RX 1762 at 5). In its summary, Intel stated RDRA Provides the Best Pentium 4 Processor Platform Now and in the Future." (R 1762 at 24). According to Pete MacWiliams ofIntel, this statement accurately summarized Intel' position as of February 2001. (MacWillams, Tr. 4935). VI. EWJEDEC PATENT POLICY Good Faith Obligations 587. Complaint Counsel rely on the EIA Legal Guides, Section C, for their contention that JEDEC participants were required to act in good faith. (CCPFF 310 citng CX 204, CX 206). 588. The EIA Legal Guides Section C, labeled "Basic Rules For Conducting Program states that " (a)ll EIA standardization programs shall be conducted in accordance with the following rules: (1) They shall be carried on in good faith under policies and procedures which wil assure fairness and unrestricted participation; . . . " (CX 204 at 5; CX 202 at 6 (earlier version of same document)). 589. Section C continues by requiring that participation be extended to all techncally qualified members of the industry and that programs serve the public interest objectives ofEIA. (CX 204 at 5). The balance of Section C prohibits collusion and price fixing and limits representatives to techncal personnel without marketing responsibilities. (CX 204 at 5). 590. The EIA Legal Guides explicitly address patents in Section B, which states that (s)tandards are proposed or adopted by EIA without regard to whether their proposal or adoption may in any way involve patents on articles, materials, or processes. " (CX 205 at 4). 591. Given the context of Section C, especially when compared with Section B , it is apparent that the "good faith duty" is not directed to individual members, but rather is a general directive to the administrators who "conduct" the EIA' s standardization activities, directing them to adopt "policies and procedures which wil assure fairness and unrestricted participation. (See CX 204 at 5). 592. Complaint Counsel rely on "An Overview of JEDEC Patent Policy" wrtten by John Kelly and dated March 26, 2002 to further support their contention that a good faith duty required Respondent to disclose intellectual property. (CCPFF 310 citing CX 449). 593. This 2002 Overview is not persuasive in interpreting JEDEC patent policy during the time period at issue as it was written after the fact and cites JEDEC Manual 21K, published after Rambus withdrew from JEDEC. (See CX 449 at 1-2). 594. No contemporaneous documents were provided by Complaint Counsel to support their contention that JEDEC members had a duty of good faith or a duty to comply with the spirit of the patent policy. (See CCPFF 310-315). 595. At trial, JEDEC members testified that there was a good faith duty imposed on members ofJEDEC. (1. Kelly, Tr. 1841 ("companies need to participate in the process openly and honestly and fairly and in good faith and not in bad faith, because bad faith undermines the confdence of everyone in the process. "); G. Kelley, Tr. 2397 ("my mind translated (good faith) to fair treatment for all members ); Rhoden, Tr. 305-06 ("The term ' good faith' as used in (the Legal Guides) is that the people. . . are coming under the premise that they re going to . . . work toward the benefit of the end user of the industry itself, and operating in good faith means that you would expect other people to do the same thing. ); Sussman, Tr. 1330 ("Good faith, we re all competitors, we re all about ready to dice each other in the marketplace, but seeing we re talking about or about to talk on intellectual property, I trust you to do something, and I expect that same set of trust back." )). 596. Despite their trial testimony, some JEDEC members, including those in leadership positions, did not always conduct themselves in a manner consistent with a duty to disclose intellectual property or to act in good faith. (See F. 686-717). For example, G. Kelley, ffM representative and JC 42.3 Commttee Chair, on multiple occasions, indicated that ffM would not disclose patents to JEDEC (F. 691-93) and JEDEC Chairman Rhoden failed to disclose a patent application on which he was listed as an inventor. (F. 711- 17). 597. Viewing the trial testimony in conjunction with the conduct ofJEDEC members and leaders, there is not suffcient evidence to find a duty of good faith imposed on participants of JEDEC. (F. 587-96). Open Standards 598. The goal ofJEDEC is to develop open standards. (CX 419; Rhoden, Tr. 301 , 536; 1. Kelly, Tr. 1776- , 1782, 1787). 599. Open standards may, and often do, include patented features or technologies. The EIA Legal Guides, which governed JEDEC, provide that "(s)tandards are proposed or adopted by EIA without regard to whether their proposal or adoption may in any way involve patents on articles, materials, or processes. (See CX 204 at 4; CX 206 at 6; 1. Kelly, Tr. 1829-30). 600. JEDEC Chairman Rhoden testified that "open standards inside of JEDEC essentially means that we want to set up a mechanism where everyone can participate that wants to, and in the end, the end product is then available to everybody in the world. So, open participation, open accessability, if you will. " (Rhoden, Tr. 300-01). 601. JEDEC does not include known patented material in JEDEC standards without written assurances from the owner of the intellectual property that it wil grant licenses, reasonable and nondiscriminatory ("RA") terms to all applicants. (CX 203A at 11; CX 208 at 19; JX 54 at 9; CX 2191 at 8; see also 1536-81). 602. JEDEC does not determine what is a reasonable royalty rate because JEDEC does not "have the expertise to be able to determne what s commercially reasonable in the context of any industry, no less semiconductors. .. That expertise resides in the industry. So, that's why in the first instance we leave it to the parties themselves to work out what's reasonable. (1. Kelly, Tr. 1882-83; see also CX 2089 at 174-75 (Meyer, Infneon Trial Tr. )). 603. Determination of a reasonable royalty rate is left to negotiation and market forces or the courts. (CX 2089 at 174-75 (Meyer, Infneon Trial Tr. ); 1. Kelly, Tr. 1882- 2073-74). 604. Hans Wiggers, a JEDEC representative from Hewlett-Packard in the early to mid- 1990' , testified that it was his understanding that the JEDEC patent policy was that, as long as a company licensed its patents after they issued on RA terms to all interested parties, the company had no obligation to disclose its intellectual property. (Wiggers, Tr. 10591). 605. In 1996, in its correspondence to the Commssion regarding the Dell case, EIA recognized that by "allowing standards based on patents, American consumers are assured of standards that reflect the latest innovation and high technology the great techncal minds of this country can deliver. . . . (T)here is a positive and pro-competitive benefit to incorporating intellectual property in standards." (R 669 at 2-3). Manuals JEP 21- 606. JEDEC Manual of Organization and Procedure 21-H ("JEP 21- ), dated July 1988, which was stil in effect when Rambus joined JEDEC in 1992, contains the following legend: "Electronic Industries Association. Engineering Department." (CX 205 at 1). 607. JEP 21-H includes in Appendix D a non-liability disclaimer to be incorporated into JEDEC standards. This disclaimer states that "JEDEC standards are adopted without regard to whether or not their adoption may involve patents on articles, materials or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the Standards. " (CX 205 at 20). 608. JEP 21-H states that "(a)ll meetings of the JEDEC Solid State Products Engineering Council and its associated Commttees, Subcommttees, Task Groups and other units shall be conducted within the current edition ofEIA Legal Guides adopted by the EIA Board of Governors and incorporated herein by reference." (CX 205 at 14). 609. The 21-H Manual does not provide any guidance regarding intellectual property rights or an obligation to disclose patents, patent applications, or the intent to file patent applications. (See CX 205). JEP 21- 610. JEDEC Manual of Organization and Procedure 21-I ("JEP 21- ), dated October 1993 , contains the following legend: "Electronic Industries Association. Engineering Department" and displays the trademarks of both JEDEC and EIA. (CX 208 at 1). 611. Section 9. , JEP 21-I states: "(a)ll meetings of the JEDEC Solid State Products Engineering Council and its associated commttees, subcommttees, task groups and other units shall be conducted within the current edition of EIA legal guides adopted by the EIA Board Governors and incorporated herein by reference. " (CX 208 at 18). 612. Section 9. , JEP 21-I discusses the use of patented products in EIA Standards as follows: EIA and JEDEC standards and nonproduct registrations (e. package outline drawings) that require the use of patented items should be considered with great care. While there is no restriction against drafting a proposed standard in terms that include the use of patented item (FN 1) if techncal reasons justify the inclusion commttees should ensure that no program of standardization shall refer to a product on which there is a known patent unless all the relevant techncal information covered by the patent is known to the formulating commtteeL) subcommttee, or working group. If the commttee determined that the standard requires the use of patented items, then the commttee chairperson must receive a written assurance from the organization holding rights to such patents that a license wil be made available without compensation to applicants desiring to implement the standard, or written assurance that a license wil be made available to all applicants under reasonable terms and conditions that are demonstrably free of any unfair discrimination. Additionally, when a known patented item is referred to in an EINJEDEC standard, a cautionary note, as outlined in this document, shall appear in the EINJEDEC standard (see 9. 1.). All correspondence between the patent holder and the formulating commttee, subcommttee, or working group, including a copy of the wrtten assurance from the patent holder discussed above, shall be transmitted to the EIA Engineering Department and the EIA General Counsel at the earliest possible time and, in any case before the standard is otherwise ready for subcommttee or commttee ballot circulation. (See the Style Manual, EP- A, 3.4 for the required language in an EIA Standard that cites a product with a known patent.) (FN 1): For the purpose of this policy, the word "patented" also includes items and processes for which a patent has been applied and may be pending. (CX 208 at 19). 613. Section 9. 3 of JEP 21- I describes the requirements of incorporating known patented products in EINJEDEC standards - namely, that all techncal information should be known and RA assurances obtained. (CX 208 at 19). 614. Although this section, through a footnote, defines "patented" to include pending patents, the section also expressly recognizes that it only applies to "known patents." (CX 208 19). 615. This section does not impose an obligation to disclose intellectual property. Rather it explains the procedure and information necessary for including a known patent into a standard. (CX 208 at 19). 616. Section 9. , JEP 21-1 states: 1 Committee Responsibilty Concerning Intellectual Property The Chairperson of any JEDEC commttee, subcommttee, or working group must call to the attention of all those present the requirements contained in the EIA Legal Guides, and call attention to the obligation of all participants to inform the meeting of any knowledge they may have of any patents, or pending patents, that might be involved in the work they are undertaking. Appendix E (Legal Guidelines Summary) provides copies of view graphs that should be used at the beginnng of the meeting to satisfy this requirement. Additionally, all participants must be asked to read the statement on the back of each EIA Sign-in/Attendance Roster. (CX 208 at 19). 617. Section 9. 3. 1 of JEP 21- I is ambiguous because it refers to the EIA Legal Guides immediately before and immediately after mentioning an "obligation to inform the meeting of. . . patents, or pending patents. " (CX 208 at 19). The EIA Legal Guides to which this section refers however, do not support such an obligation. (See CX 208 at 26-29; CX 204). 618. To satisfy the requirement to call attention to the obligation to disclose patents and patent applications, section 9. 1 refers to Appendix E and the EIA sign-in/attendance roster. (CX 208 at 19). 619. Appendix E, JEP 21-I explains that " (t)he following material may be made into viewgraphs that can be shown at JEDEC meetings to summarize EIA legal guidelines covering the areas of improper activities and programs, patents, and copyright protection. More detailed information in each area is available from the EIA Legal Offce. " (CX 208 at 26). 620. Appendix E, JEP 21-I includes the following procedure for incorporating patented technology in standards: EIA/JEDEC PATENT POLICY SUMRY Standards that call for use of a patented item or process may not be considered by a JEDEC commttee unless all of the relevant technical information covered by the patent or pending patent is known to the commttee, subcommttee, or working group. In addition, the commttee Chairperson must have received written notice from the patent holder or applicant that one of the following conditions prevails: * A license shall be made available without charge to applicants desiring to utilize the patent for the purpose implementing the standards(s), * A license shall be made available to applicants under reasonable terms and conditions that are demonstrably free of any unfair discrimination. In either case, the terms and conditions of the license must be submitted to the EIA General Counsel for review. An appropriate footnote shall be included in the standard identifying the patented item and describing the conditions under which the patent holder wil grant a license. (CX 208 at 27). 621. Appendix E of JEP 21- I, which describes itself as an "EINJEDEC Patent Policy Summary," indicates that "a patented item or process may not be considered. . . unless all ofthe relevant techncal information covered by the patent or pending patent is known" and that assurances must be obtained. (CX 208 at 27). This statement does not impose a duty to disclose upon members. Rather, it explains the procedure to follow in utilizing known patented items consistent with the requirements of section 9. 622. Appendix E does not distinguish between EIA and JEDEC patent policies; it is labeled the "EINJEDEC patent policy." (CX 208 at 27). 623. Appendix F, JEP 21-I states: Fl. PATENT POLICY APPLICATION GUIDELINES The following points describe the application of the JEDEC patent policy: * Commttee discussion of pending or existing patents is a permssible activity and is encouraged when the commttee feels that the patented item or process represents the best techncal basis for a standard. * Discussion of a pending or existing patent does not constitute an acknowledgment of the validity of the patent, because validity is based on prior art and determination of who first made the invention or applied for the patent. The commttee s concern is with techncal merits and whether the techncal proposal is a sound basis for standardization. * By its terms, the EIA Patent Policy applies with equal force to situations involving: 1) the discovery of patents that may be required for use of a standard subsequent to its adoption, and 2) the initial issuance of a patent after the adoption of a standard. Once disclosure is made, the holder is obligated to provide the same assurances to EIA as are required in situations where patents exist or are known prior to approval of a proposed standard. Thus, if notice is given of a patent that may be required for use of an already approved EIA Standard, a standards developer may wish to make it clear to other standards-making participants that the JEDEC procedures require the patent holder to provide the assurances contained in the Patent Policy or suffer the withdrawal of EIA' s approval of the standard as an EIA Standard and ultimately, as an American National Standard. (CX 208 at 29). 624. Appendix F of JEP 21-I recognizes that (1) discussion of intellectual property issues is allowed, (2) a disclaimer that such discussions do not constitute an acknowledgment of the validity of the patents, and (3) the policy applies to (a) the discovery of patents after a standard is adopted and (b) the issuance of a patent after the standard is issued. This section makes clear that EIA will pursue the same procedure in these situations as if the patent were known during the standardization procedure. Finally, this section provides the penalty for failure to provide assurances: that the standard may be withdrawn. (CX 208 at 29). 625. At the September 1993 JC 42. 3 meeting, the commttee chairman showed a viewgraph containing proposed language from an appendix to the not-yet-published JEP 21- manual. This viewgraph was expressly marked "DRAT" and contained a footnote stating that the "material is a proposed revision" that "has not been approved by JEDEC." (JX 17 at 12). Although this draft did refer to a "patent or pending patent " it did not mention an obligation to disclose intellectual property, nor did it instruct the chairperson to call attention to such an obligation. (JX 17 at 12). 626. The commttee chairman also showed a different draft ofthe 21-I Manual at the December 1992 JEDEC JC 42. 3 meeting similarly marked as a draft. (Crisp, Tr. 2983-88; see 14 at 3 , 25). 627. It is not clear that JEP 21-I was ever formally adopted by JEDEC. John Kelly, EIA Legal Counsel, testified that JEP 21-I needed a final stamp of approval from EIA' s EDEC and that he did not know whether JEP 21-I ever received that approval. (1. Kelly, Tr. 2104-05). 628. Complaint Counsel did not provide suffcient evidence to find that JEP 21-I received the approval from EDEC necessary for JEP 21-I to become the controllng manual. 629. Rambus did not receive a copy of21-I until the summer of 1995. (Crisp, Tr. 3475). 630. JEDEC did not maintain a log of who received copies of manuals and it was not the practice of JEDEC to mail all documents as they were revised. (CX 317 at 1; Grossmeier, Tr. 10944-45). 631. Although JEP 21- I refers to an obligation to disclose intellectual property, it does not provide a basis for the obligation, or a discussion of the extent of the obligation. Moreover, it is facially inconsistent with the EIA sections to which it refers. (See CX 208 at 19). 632. JEP 21-I is ambiguous and can not be construed to impose a clear obligation to disclose intellectual property. (See CX 208). EIA Legal Guides 633. The EIA Legal Guides include a non-liability disclaimer that " (s)tandards are proposed or adopted by EIA without regard to whether their proposal or adoption may in any way involve patents on aricles, materials, or processes. By such action, EIA does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting EIA standards. " (CX 204 at 4). 634. The EIA Legal Guides do not contain any specific reference to any disclosure obligation in connection with a member s intellectual property. (See CX 204). EP- F and EP- 635. The October 1981 EIA manual known as "EP- F" provides the following procedure for using patented items in standards: Reference to Patented Products In EIA Standards Requirements in EIA Standards which call for the use of patented items should be avoided. No program of standardization shall refer to a product on which there is a known patent unless all the techncal information covered by the patent is known to the Formulating commttee, subcommttee, or working group. The Commttee Chairman must have also received a written expression from the patent holder that he is wiling to license applicants under reasonable terms and conditions that are demonstrably free of any unfair discrimination. Additionally, when a known patented item is referred to in an EIA Standard, a Caution Notice, as outlined in the Style Manual, EP- , shall appear in the EIA Standard. (CX 203A at 11). 636. The 1990 EIA manual known as "EP-7 -A" provides information about obtaining RA assurances: 3.4 Patented Items or Processes Avoid requirements in EIA standards that call for the exclusive use of a patented item or process. No program (of) standardization shall refer to a patented item or process unless all of the techncal information covered by the patent is known to the formulating commttee or working group, and the commttee chairman has received a written expression from the patent holder that one of the following conditions prevails: (1) a license shall be made available without charge to applicants desiring to utilize the patent for the purpose of implementing the standard, or (2) a license shall be made available to applicants under reasonable terms and conditions that are demonstrably free of any unfair discrimination. . . . An appropriate footnote shall be included in the standard identifying the patented item and describing the conditions under which the patent holder will grant a license (see 6. 2). (JX 54 at 9- 10). 637. The EP- F manual and the EP- A manual, which were in effect when Rambus joined JEDEC, both contain a requirement that no standard shall refer to a product on which there is a known patent unless all the techncal information covered by the patent is known to the commttee or working group. (CX 203A at 11- 12; JX 54 at 9). 638. The EP- F manual and the EP- A manual make no explicit reference to an obligation on the part ofEIA members or others to disclose patents or patent applications. (See 1. Kelly, Tr. 1824- , 1905- 2082-83; CX 203A; JX 54). ANSI Patent Policy 639. The ANSI Patent Policy Guidelines were attached to the May 1992 JC 42. 3 meeting minutes and were circulated to JC 42. 3 members in 1994. (CX 34 at 19). 640. 1. Kelly circulated the ANSI Guidelines to JC 42. 3 members in 1994 because he thought they provided insight into the proper interpretation of the EIA and JEDEC patent policy. (1. Kelly, Tr. 1950). 641. J. Kelly was a member of the ANSI patent policy working group from 1990 until 2002 and was personally involved in the discussions and deliberations leading to the final approval of the ANSI guidelines. (1. Kelly, Tr. 1950-51). 642. At the time that the ANSI Guidelines were circulated to JC 42. 3 members in 1994 the language of the EIA patent policy and the ANSI patent policy was essentially identical. (1. Kelly, Tr. 2077-78). 643. The ANSI patent policy guidelines " seek to encourage the early disclosure and identification of patents that may relate to standards under development." (R 1712 at 6). 644. The ANSI patent policy guidelines specify that "it is desirable to encourage disclosure of as much information as possible concerning the patent, including the identity of the patent holder, the patent' s number, and information regarding precisely how it may relate to the standard being developed." (RX 1712 at 8). 645. The ANSI patent policy guidelines indicate that "a standards developer may wish to encourage participants to disclose the existence of pending US. patent applications relating to a standard under development. Of course, in such a situation the extent of any disclosure may be more circumscribed due to the possible need for confdentiality and uncertainty as to whether an application will mature into a patent and what its claimed scope wil ultimately be." (R 1712 at 8). Committee Forms Membership Application 646. The application completed by Rambus upon joining JEDEC does not impose an obligation on members to disclose intellectual property. (CX 601 at 1-2). Indeed, there is no mention of intellectual property in the application. (CX 601 at 1-2). 647. Complaint Counsel did not present suffcient evidence to support their allegation (Complaint,- 15) that the JEDEC membership application included an obligation to abide by JEDEC's rules. (See CX 601). Meeting Attendance Roster (Sign-In Sheet) 648. Participants at 'each JEDEC meeting were required to record their names on the sign-in sheet or meeting attendance roster. (CX 306; CX 3136 at 135). 649. Sign-in/attendance rosters were not considered an "offcial form" because they "vary from division to division and almost year-to-year." (CX 317 at 1). 650. The sign-in/attendance roster states in relevant part: " Subjects involving patentable or patented items shall conform to EIA Policy (reverse side). Consult the EIA General Counsel about any doubtful question. " (CX 306 at 1). 651. The sign-in/attendance roster states on the reverse side: REFERENCE TO PATENTED PRODUCTS IN EIA STANDARDS Requirements in EIA Standards that call for the use of patented items should be considered with great care. While there is no objection in principle to drafting a proposed standard in terms that include the use of a patented item, if it is considered that techncal reasons justify this approach, Commttee Chairmen should ensure that no program of standardization shall refer to a product on which there is a known patent unless all relevant and reasonably necessary techncal information covered by the patent is known to the formulating commttee, subcommttee, or working group. The Committee Chairmen must have also received a written assurance from the patent holder that a license wil be made available without compensation to the applicants desiring to utilize the license for the purpose of implementing the standard; or a written assurance that a license wil be made available to applicants under reasonable terms and conditions that are demonstrably free of any unfair discrimination. Additionally, when a known patent item is referred to in an EIA Standard a Caution Notice, as outlined in the Style Manual, EP- , shall appear in the EIA Standard. All correspondence between the patent holder and the formulating commttee, subcommttee, or working group, including a copy of the written assurance from the patent holder mentioned above, shall be transmitted to the EIA Engineering Department and the EIA General Counsel at the earliest possible time, but no later than the point when the EIA Standard Proposal is ready for Commttee ballot. (See the Style Manual for EIA Publications, EP- , Section 3. 4 for required language in an EIA Standard that cites a known patented product). (CX 306 at 2). 652. The sign-in/attendance roster was modified to include the term "patentable" in the early 1990's around the time of the Wang litigation. (1. Kelly, Tr. 1934-35). For discussion of the Wang litigation, see infra F. 689-90. 653. The reference to "patentable or patented items" on the fron page ofthe signin/ attendance roster is ambiguous because it refers to the EIA guides. The EIA Guides which appear on the reverse side, however, apply only to issued patents. (CX 306 (EIA Legal Guides use the terms: "patented items " " known patent " " techncal information covered by the patent and "patent holder )). Committee Ballots 654. The commttee ballots used by JEDEC to record votes on standardization proposals contained a variety of voting options, including an option which read: "I do not approve the content of the (ballot topic). Attached are my detailed reason(s) for this disapproval. (We need your reason(s) in order to understand your view on this matter.) MAATORY." (CX 252A at 2). 655. The commttee ballots also stated: "If anyone receiving this ballot is aware of patents involving this ballot, please alert the Commttee accordingly during your voting response. (CX 252A at 2). 656. When this language regarding patents was first added to the commttee ballots, a JEDEC member asked during a JEDEC meeting about the purpose of the new language. The minutes of the JC 42. 1 meeting held on September 13 , 1989 state that: Council discussed patent issue at their June meting (sic J at the request ofJC-42. 3. The result was not to change EIA legal requirements as outlined in document EP- , but to add some wording on JEDEC ballot voting sheets about informing the Commttee if any patent covers the balloted material. TI was concerned that Commttee members could be held liable if they didn t inform Commttee members correctly on patent matters. Committee responded that the question was added on ballot voting sheets for information only and was not going to be checked to see who said what. (CX 3 at 6). 657. Sussman explained the options on ballots as follows: Yeah, I can approve the ballot. I can not approve the ballot. I can abstain on the ballot. I can approve it with comments. And the bottom one is saying that regardless of what I do, ignoring any of the above things, I can also point out that I know of or I believe there might be a patent that could read on the - on this concept, on this ballot. (Sussman, Tr. 1391). 658. It is clear from the plain language of the commttee ballot that a no vote mandates an explanation, while patent disclosure is only requested on a voluntary basis. (See CX 252 at 2). Members' Manual 659. The introduction to the "JC 42 Members' Manual " dated September 1994, states that " (tJhis manual was compiled to assist new (and established) members in achieving full effectivenes (sic) in the standards making process." (RX 507 at 2). 660. The members' manual was a document created by Jim Townsend, JC 42 Chairman and does not display the JEDEC or EIA trademarks or otherwise purport to be an offcial EIA publication. (RX 507). 661. The members' manual was not approved by the JEDEC Council and the meeting minutes indicate that " (s)ome of this material is not approved by JEDEC . . . It should be clear that this manual is not a publication of JEDEC because it has not been balloted by Commttee or Council." (JX 31 at 4). 662. The members' manual patent policy section states: "Commttees adhere rigidly to the EIA patent policy as given in EIA publication EP- A, August 1990, Pars. 3.4 & 3. 5 and in EIA Publication EP- , October 1981 , Par 8. 3 which require intellectual property disclosure and discussion if proposed standards are affected." (RX 507 at 15). 663. The members' manual states that " (a)ll first presentations must be accompanied by wrtten handouts for all companies present giving complete details of the material being presented. In addition, the presenter must reveal any known or expected patents, within his company, on the material presented. " (RX 507 at 15). 664. The members' manual is ambiguous because it states that the commttee "adheres rigidly to the EIA patent policy" which it describes as requiring intellectual property disclosure. (R 507 at 15). However, the EIA patent policy to which it refers does not require disclosure of intellectual property. (See F. 633-38). 665. The members' manual is also ambiguous because the patent policy section suggests a requirement of intellectual property disclosure without indicating who is required to disclose while the "First Presentation" section limits disclosure to those making presentations. (See 507 at 15). Patent Tracking List 666. A patent tracking list, which was a compilation of patents and patent applications of which Townsend had been made aware through the course of the work inside JEDEC, was maintained by Chairman Townsend. (Rhoden, Tr. 325; Sussman, Tr. 1355). 667. Townsend "began the patent tracking list. . . in May of 1991." (G. Kelley, Tr. 2407). The patent tracking list had multiple purposes, including record-keeping, a reminder to other participants of the patent issues that were on, and as an educational tool for those who were newcomers to the commttee. (G. Kelley, Tr. 2407-08). 668. The patent tracking list was an informal, incomplete list of patents and patent applications disclosed to the JC 42. 3 commttee. (G. Kelley, Tr. 2408). Rhoden explained that it was Mr. Townsend' s personal list, and I'm not sure that everyhing was included in it." (Rhoden, Tr. 334-35). 669. The cover sheet accompanying the patent tracking list included the term "patentable matters" which JEDEC Chairman Rhoden testified he understood to mean "anything that would be in the patent process. Essentially if you believe that you have ownership of a particular topic or a particular item, then that is what he s referring to. Patentable, whether a patent had actually been applied for or not." (Roden, Tr. 336). Contemporaneous Correspondence The McGhee Memorandum 670. ETSI is the European Telecommunications Standards Institute. As indicated in the EIA letter to the Federal Trade Commssion commenting on the Dell consent order, ETSI undertook efforts "to force compulsory licensing on an extraterritorial basis." (RX 669 at 3). 671. On March 29, 1994, JEDEC Secretary Ken McGhee sent a memorandum to JC 42 Chairman Jim Townsend regarding the "ETSI Policy within JEDEC" that stated that JEDEC' legal counsel had said that: (H)e didn t think it was a good idea to require people at JEDEC standards meetings to sign a document assuring anything about their company patent rights for the following reasons: (1) It would have a chillng effect at future meetings (2) A general assurance wouldn t be worth that much anyway (3) It needs to come from a VP or higher within the company - engineers can t sign such documents (4) It would need to be done at each meeting slowing down the business at hand. (R 486 at 1). Correspondence Regarding the Dell Consent Agreement 672. The Commssion issued a complaint and entered into a consent agreement with Dell Computer Corporation ("Dell") which prohibited Dell from enforcing its patent rights against computer manufacturers using the VL-bus. The Commssion placed upon the public record the executed consent decree with arequest for public comments. In re Dell Computer Corp. , 121 C. 616, 619 (May 1996). 673. In January 1996, a letter was submitted to the FTC on behalfofEIA and its unincorporated divisions and departments (including JEDEC), as well as on behalf of the Telecommunications Industries Association ("TIA"), in response to the Dell action. EIA General Counsel 1. Kelly s name and title appear in the signature block. (R 669 at 5; 1. Kelly, Tr. 2092- 93). 674. The EIA's January 1996 comment letter to the CommSsion states in relevant part: Both EIA and TIA encourage the early, voluntary disclosure of patents that relate to the standards in work. Commttee and subcommttee chairs ask during the meetings whether any parties are aware of any patents that relate to the contributions under discussion. When potential patents are disclosed, EIA and TIA staff contact the patent holders to ensure that essential patents wil be licensed in accordance with the EIA, TIA and ANSI IPR policies. (R 669 at 3). 675. The EIA's January 1996 comment letter to the FTC clarifies that the "EIA, TIA and ANSI IPR policies relate to essential patents" and that "even if knowledge of a patent comes later in time due to the pending status of the patent while the standard was being created, the important issue is the license availability to all parties on reasonable, non-discriminatory terms." (RX 669 4). 676. In July 1996, the FTC, in a letter signed by FTC Secretary Donald Clark, responded to the EIA's January 1996 letter. The FTC's letter states in relevant part that: "EIA and TIA, following ANSI procedures, encourage the early, voluntary disclosure of patents, but do not require a certification by participating companies regarding potentially conficting patent interests." (R 740 at 1). 677. The FTC's statement distinguishing the EIA's patent policy from the policy at issue in the Dell matter, and the FTC' s explanation that the differences in the two patent policies meant that the "expectations of participants in the two standard-setting processes differ " indicate that FTC Secretary Clark interpreted the EIA's January 1996 letter to mean that the EIA encouraged but did not require, the disclosure by members of intellectual property interests. (RX 740 at 2; see RX 669 at 2). 678. On July 10, 1996, JEDEC Secretary Kenneth McGhee sent a memorandum to Jim Townsend, addressed to "JEDEC Council Members and Alternates " regarding the FTC' s Final Consent Order in the Dell case, which stated in part that: "the FTC emphasized that it was not intending to signal a general duty to search for patents when a company engages in standards setting (ANSI and EIA do however, encourage early, voluntary disclosure of any known essential patents.)" (R 742 at 1). 679. These letters clearly state JEDEC' s patent policy was limited to encouraging early, voluntary disclosure of any known essential patents. (R 669; RX 742). Correspondence Regarding Micron Disclosure 680. On January 28 2000, Micron drafed a written disclosure of a patent application relating to a proposed standard under consideration in the JC 42.4 subcommttee. (R 1559 at 2). 681. On February 1 , 2000, JEDEC Secretar McGhee sent an email to members of the subcommttee stating, "I would like to point out that this letter is well intentioned, but lacks a patent number, so it does not complete the requirements for JEDEC patent policy. If, however, a follow-up letter is issued after the patent is issued, then it would comply with JEDEC' s patent policy. " (RX 1559 at 1). 682. Upon receiving McGhee s email that Micron had not complied with the patent policy because Micron s disclosure did not include a patent number term, Terr Walther of Micron caused the matter to be placed on the agenda for the next JEDEC board meeting. (RX 1568 25). 683. The minutes of the February 2000 meeting ofthe JEDEC Board of Directors state: Disclosure on Patents Pending Mr. Walther noted that Micron had sent a letter indicating they have patents pending on items that may affect commttee standards. The issue was whether companies should make public that a patent is pending. The BoD discussed it and noted they encourage companies to make this kind of disclosures even though they were not required by JEDEC by laws. (RX 1570 at 13). 684. In an email written a few days after the February 2000 board meeting, JEDEC Secretary Ken McGhee, who had been present at the meeting (R 1570 at 2), reported to a JEDEC subcommittee that the JEDEC Board had discussed Micron s "patent pending disclosure. Secretary McGhee stated that: The JEDEC patent policy concerns items that are known to be patented that are included in JEDEC standards. Disclosure of patents is a very big issue for Commttee members and cannot be required of members at meetings. However, if a company gives early disclosure on a patent they are working on, it definitely gives a lot of assurance to the Commttee members regarding development of any standards affecting it. Therefore, in Micron s letter, by giving early disclosure, they have gone one step beyond the patent policy and have complied with the spirit of the law. JEDEC encourages this type of activity from any member. (R 1585 at 1). 685. Disclosure of patent applications, or pending patents, was "not required" by JEDEC in 2000 even though disclosure was "encouraged." (RX 1570 at 13). The "spirit of the law" is 100 to disclose patent applications even though disclosure "cannot be required of members." (RX 1585 at 1). Conduct of Parties in JEDEC SEEQ Issue 686. A company named SEEQ proposed a JEDEC standard called silicon signature. (Sussman, Tr. 1338). SEEQ owned two patents related to the technology, but disclosed and offered to license only one. (Sussman, Tr. 1338-39 (SEEQ "was tellng us about silicon signature and offering it as a royalty-free license to anyone who wanted it, hoping that just as soon as we standardized this, the second patent, which would be die trace, which he had not said anything about, but because it was al ost identical, would be insisted upon by the customers, and (SEEQ) could put a tax on us. )). 687. Upon learning of SEEQ' s second patent, the commttee was willing to standardize the SEEQ technology, provided that SEEQ agreed to reasonable licensing terms. (CX 3 at 4). 688. When the commttee learned that the second patent was not included in the patent release, JEDEC chose to standardize on a different technology. (Sussman, Tr. 1338-39). WANG Litigation 689. The Wang litigation involved allegations of a failure to disclosure a patent application on the part of a company that had promoted its technology for standardization. (CX 711 at 188). Wang was "part of the commttee, they had helped set a standard, and then they went out and enforced their patents against everybody in the industry who used a SIM module. " (Wiliams, Tr. 787). 690. Wang failed to disclose a patent relating to memory modules and later attempted to enforce the patent against the industry which "ended up in a rather lengthy litigation, crossed multiple houses and cost the industry millons of dollars before the patent was found to be invalid." (Sussman, Tr. 1338; see also Landgraf, Tr. 1697-98; JX 20 at 4). ffM' s Patent Position 691. The minutes of the March 1993 meeting ofJC 42. 3 state in part that "ffM noted that their view has been to ignore (the) patent disclosure rule because their attorneys have advised them that ifthey do then a listing may be construed as complete. " (JX 15 at 6). 692. In an August 1993 memo to JEDEC leaders entitled "BGA PatentlLicense Rights ffM JEDEC representative (and JEDEC 42. 3 subcommttee chair) Gordon Kelley stated that: 101 ffM Intellectual Property Law attorney s (sic) have informed me that we wil not use JEDEC as a forum for discussing this subject. It is the responsibility ofthe producer to evaluate the subject and to workout the proper use of rights. So, I can not confrm or deny any IPL rights. (RX 420 at 2). 693. The December 1993 JEDEC 42. 3 minutes state in part that " (a)s a side issue, ffM noted that in the future they wil not come to the Commttee with a list of applicable patents on standards proposals. It is up to the user of the standard to discover which patents apply." (JX 18 at 8). 694. Between December 1993 and December 1995 (Rambus s last meeting), no ffM patent or patent application was added to the "patent tracking list" maintained by JC 42 Chairman Jim Townsend. (See JX 18 at 14-21; JX 19 at 17-23; JX 20 at 15- 18; JX 21 at 14- 18; JX 22 at 12- 17; JX 25 at 18-26; JX 26 at 15-24; JX 27 at 20-25; JX 28 at 12-23). 695. Regarding ffM, Cray representative Grossmeier testified that "ffM said they didn feel they had the resources to review their entire patent portfolio every time a proposal was made to see ifthere was anything in there that was applicable. So, they would not disclose any patents that they had that were related to the standard." (Grossmeier, Tr. 10956). His opinion was that I think they all understood the policy. I think they just elected not to practice it." (Grossmeier Tr. 10956-57). 696. A Hewlett-Packard representative to JEDEC, Hans Wiggers, testified that he had attended a JEDEC meeting where ffM representative and Commttee Chair Gordon Kelley said: Look, I cannot disclose - my company would not let me disclose all the patents that ffM is working on because, you know, I just can do that. The only thing we wil do is we wil follow the JEDEC guidelines and - or rules on whatever and we wil make them available. (Wiggers, Tr. 10592-93). 697. This is consistent with Gordon Kelley s testimony. G. Kelley testified that he did not disclose ffM patents relating to "toggle mode" in 1990 in part because ffM was "prepared to meet the requirements of the JEDEC commttee" to license the patents on reasonable and nondiscriminatory terms. (G. Kelley, Tr. 2715- 16). 698. Complaint Counsel did not present suffcient evidence from which to find that ffM was ever sanctioned for announcing its refusal to disclose the company s intellectual property. 102 Hewlett Packard' s Patent Position 699. Hewlett Packard' s representative, Wiggers, testified that when JC 42. 3 Chair G. Kelley stated his position at the JEDEC meeting regarding ffM' s nondisclosure of patent applications, Wiggers told the meeting attendees that HP took the same position. (Wiggers Tr. 10593-94). 700. Complaint Counsel did not present suffcient evidence from which to find that Hewlett-Packard was ever sanctioned for announcing its refusal to disclose the company intellectual property. Texas Instruments' QUAD CAS Issue 701. On March 9, 1994, Texas Instruments presented a letter to JEDEC regarding ambiguities in the JEDEC patent policy. This letter began "Texas Instruments believes that the JC 42. 3 Commttee on RA Memories should review and clarify its interpretation of the JEDEC Patent Policy." The letter further states that "TI is concerned that the commttee, or at least some of its members, have interpreted the scope of the JEDEC Patent Policy in a manner that is not only incorrect but unworkable as well. The resulting confsion has made it impossible for TI and other members to determine the appropriate course of conduct. " (CX 352 at 1). 702. A memorandum to JC 42 commttee members dated May 12, 1994 says that TI's request for clarification of the patent policy was referred to EIA's legal counsel 1. Kelly for response. The memorandum attached a copy of 1. Kelly s response. (CX 355 at 1). 703. John Kelly s response indicates that "(w)ritten assurances must be provided by the patent holder when it appears to the commttee that the candidate standard may require the use of a patented invention. " (CX 355 at 2 (emphasis in original)). 704. The meeting minutes indicate that at the close of a discussion on patents at the March 1994 Commttee meeting, the commttee felt the patent policy was clear and that discussion would be closed on the subject. (JX 19 at 4-5; Kellogg, Tr. 5028-30). 705. Gordon Kelley indicated: "I believe that the litigation between Micron and Texas Instruments was resolved, and I believe that the ballots that were on hold were removed from hold and the ballots that were in recision were reconstituted." (G. Kelley, Tr. 2483). In addition he stated that Texas Instruments "apologized for their representative who had not disclosed - I personally know that they removed him from the commttee, he did not come back, and they settled their dispute with Micron and as far as the commttee was concerned, the issue was at this point resolved. " (G. Kelley, Tr. 2485). 706. Cray representative Grossmeier testified that "some members agreed that (TI) didn 103 need to (disclose) and other(s) felt that they were in violation ofthe JEDEC policy by not (disclosing)." (Grossmeier, Tr. 10955). 707. This is clear evidence that by 1994, the patent policy was ambiguous. Indeed, in 1994 Texas Instruments explicitly recognized the "confsion" created when some members of the commttee "interpreted the scope of the JEDEC Patent Policy in a manner that is not only incorrect but unworkable as well." (CX 352 at 1). Micron s Presentation on Burst EDO 708. Brett Willams, of Micron, put together a presentation on Burst EDO that was presented at a January 1995 JEDEC DRA task group meeting. (JX 23 at 68-77; Wiliams, Tr. 825-26). Wiliams was present at the meeting and was aware that Micron s Burst EDO patent application, on which he was a named inventor, was not on the patent tracking list. (JX 23 at 1; Wiliams, Tr. 963-64). Nevertheless, Wiliams did not disclose the pending patent application on Burst EDO in connection with that presentation and vote. (Wiliams, Tr. 936-37; see RX 585 at 4). 709. It was not until April 1996 that Micron s Burst EDO patent application was disclosed to JEDEC when Micron offered to license the patents under reasonable terms and conditions, demonstrably free of any unfair discrimination, if the patents were issued and were required for use of the standard. (CX 364; Willams, Tr. 937). 710. At trial, Willams was questioned about the potential perception of his actions: Q: Okay, So once the patent issued in June of ' , if somebody had gone back and looked at that patent, they would have seen - by just looking at the patent, they would have seen, well, Micron cited as prior art early JEDEC meetings, and Micron applied for the patent in December ' after some of the early meetings and before - right before the January ' presentation that you and Mr. Fusco attended, and the patent issued in June of ' , and Micron made the disclosure to JEDEC in April of ' 96. That's the facts they would have seen. A: Yes. Q: And to your knowledge, nobody seeing those facts, no JEDEC member, came to Micron and said, you guys acted in a way inconsistent with the JEDEC policy, did they? A: I'm not sure if anybody talked to Micron about that or not. Nobody talked to me about it. (Wiliams, Tr. 941-42. 104 Hyundai and Mitsubishi' s Presentation on SLDRAM 711. On May 24, 1995, Hyundai and Mitsubishi made presentations at a meeting of the JC 42. 3 subcommttee regarding a type of DRA known as SLDRA. (JX 26 at 10- 11; Rhoden, Tr. 469-71). The minutes note that " (t)he proposal was brought to JEDEC for a pinout standard." (JX 26 at 10). The Mitsubishi presentation showed the pinout for an SLDRA. (JX 26 at 111; Rhoden, Tr. 471). 712. At a JEDEC meeting on December 9- , 1997, the SLDRA pinout standard ballot was approved by the JC 42. 3 subcommttee. (JX 41 at 22 24; RX 1114 at 1; Rhoden, Tr. 1206- 08). 713. United States Patent No. 6 442 644 (the ' 644 patent) issued on August 27 2002. (R 2086 at 1). Among the inventors named on the patent were JEDEC representatives Hans Wiggers of Hewlett-Packard, Kevin Ryan and Terry Lee of Micron, and JEDEC Chairman Desi Rhoden, formerly of VLSI. (RX 2086 at 1). 714. Rhoden testified that claim 3 of the patent claims the SLDRA pinout that had been standardized by JEDEC. (R 2086 at 41; Rhoden, Tr. 1211). 715. The ' 644 patent claims priority to a number of provisional applications, including provisional application 60/069 092 which was filed on December 10, 1997, the very same day that the JEDEC meeting approving the SLDRA patent was being held. (RX 2086 at 1; RX 2099- 43). 716. Wiggers, Ryan and Rhoden were all present at the December 1997 JC 42. subcommttee meeting where the SLDRA pinout standard was balloted and approved. (JX 41 at 2). They were each involved in or affliated with the "SLDRA Consortium" or SLDRA Inc. , which subsequently became AM2, and was assigned the ' 644 patent. (RX 870 at 1; Rhoden, Tr. 696- , 1235; RX 2086 at 1). 717. The minutes of the meeting do not indicate that any of the three disclosed the ' 092 provisional application (see JX 41 at 22, 24), even though Rhoden testified at trial that even nonmember guest scientists or engineers from foreign countries were "absolutely" obligated to disclose patents and patent applications that were related in some general way to a subject being discussed at JEDEC. (Roden, Tr. 624-25). Trial Testimony A Policy in Transition 718. The evidence suggests an unsuccessful attempt by some members ofJEDEC to redefine the patent policy after SEEQ and Wang. (See CX 46 at 9). Complaint Counsel 105 however, did not produce evidence suffcient to find an announced, formal change in policy. 719. Some members of the commttee treated the spirit of the policy as the actual policy. Wiliams testified that between late 1991 to 1993 , " (i)t was discussed how to revise the wording to ensure that the patent policy was clear so that new members, when they came on board, would know exactly the spirit of the patent policy. " (Willams, Tr. 791). Creation of Ambiguity and Confusion Regarding the Policy 720. ffM' s representative Mark Kellogg disclosed, at least twice an intention on the part of ffM to file a patent application related to a product or feature under consideration for standardization at JEDEC. At his deposition, Kellogg testified that he did not believe the disclosure was required under the JEDEC patent policy. He contradicted this testimony at trial: A: I would appreciate a chance to clarify because there s a written policy, there was an in-process modified policy, there is an expected policy, there are - there are - so in answer to your question, this refers to the wrtten policy at the time in this document. Q: In the deposition? A: And I do apologize for differing interpretations of policy. Q: When I asked you in the deposition whether you believed your disclosure was required under the JEDEC patent policy, what JEDEC patent policy were you referencing when you answered no? A: The written policy at the time. Q: Were there more than one JEDEC patent policy that related to the obligations to disclose intent to file patent applications? A: I believe so. (Kellogg, Tr. 5306-07). 721. Cray representative Grossmeier was unclear on JEDEC' s patent disclosure rules, as evidenced by his trial testimony that in the 1991-96 time frame " (iJt was not real clear on the definition of what patents should be disclosed. Clearly if the sponsor presented information that they were developing and patenting, they would disclose it, but other parties, it was pretty vague. " (Grossmeier, Tr. 10947 (emphasis added)). 722. Intel representative Sam Calvin testified that: There was - and I don t know when it occurred or how early it occurred, but there was a concern about not only patents, but 106 applications for patents. And I'm then real foggy on this , because I knew it was an issue, but when exactly it went from an issue to understanding that to be JEDEC policy is unclear in my mind. (Calvin, Tr. 1006). 723. The JEDEC patent policy was not clear. (Kellogg, 5306 ("there s a written policy, there was an in-process modified policy, there is an expected policy ); Grossmeier, Tr. 10947 (patent policy was "not real clear. . . . it was pretty vague ); Calvin, Tr. 1006 (describing patent policy as "unclear )). This lack of clarity stemmed from an unsuccessful attempt, by some, to redefine the patent policy. Unsuccessful Efforts to Expand the Patent Policy 724. The February 1991 minutes from the 42. 5 subcommttee meeting note that Townsend made a presentation on patent issues in general and made some suggestions as to what could be done in the future to avoid these problems." (CX 13 at 4). 725. Attached to the meeting minutes were handwritten notes. These notes include section labeled "Expectations of Participants" which includes as the only expectation regarding disclosure that " (fJull disclosure of sponsors regarding restrictions on intellectual property at conceptual phase of draft standard. " (CX 13 at 31 (emphasis added)). 726. The notes include a section labeled "Possible Solutions on Intellectual Property which includes the following suggestions: Require each member and alternate, each year, to sign an affadavit that they wil disclose all knowledge of patents affecting a draft ballot. Requiring a legal statement from the sponsoring company s Intellectual Property counsel to be attached to an approved ballot when submitted to Council for final approval. Expulsion from JEDEC of a company who attempts to achieve commercial advantage from standardization if they have not disclosed at the beginnng their patent position, intention, and royalty objectives on a draft ' patent. Censure by the supplier community of any such company. Establish equivalent standards to provide royalty-free alternatives to the industry. (CX 13 at 32). 107 727. In a March 11 , 1991 letter copied to John Kelly, John Kinn, Vice President of Engineering at JEDEC, in response to a letter from Jim Townsend regarding JEDEC' s patent policy, indicated that " (t)he basic documents containing our policy on patents are: EP- , EPThe JEDEC Manual JEP-21- , and the EIA Legal Guide." (CX 317). 728. Kinn attached a draft revision of the ANSI policy, indicating that it was "arrived at following two years of discussion among legal representatives, from Standard developers and users. Many individuals feel they do not go far enough - others feel they go too far - a classic case of our inability to harmonize conficting opinions in areas outside those that must obey the laws of physics. " (CX 317 at 1). 729. Kinn noted a discussion from the previous council meeting although "no definitive conclusions were reached other than to await the results ofthe ANSI work." (CX 317 at 1). Kinn stated "I agree this issue should be continually reviewed at Council level until we arrive at the best possible policy given modern circumstances and technology. Perhaps JEDEC should sponsor a special workshop. . . and perhaps achieve a consensus on future directions for our policy. " (CX 317 at 2). 730. Meeting minutes from the May 9, 1991 JC 42. 3 meeting indicate, regarding intellectual property, that: Toshiba noted that some of the procedure documents have been issued a long time ago but because of high Committee turnover many reps don know what the policies are. Toshiba recommended that at each meeting a showing be made to explain what the intellectual property policies are. Toshiba would also like to have a note on each ballot before it goes to Council from the company lawyer. It was a Council issue, but Toshiba wanted the Commttee to deal with it. (JX 5 at 3). 731. G. Kelley, JC 42. 3 Chair, testified that "Jim Townsend had suggested that we begin to include patent applications in the concept of a patent and that was brought to the commttee in May of 1991 and the vote was taken to agree that the commttee would work to that new definition of patents " although there is no evidence of such a vote in the May 1991 minutes. (G. Kelley, Tr. 2691; see JX 5). 732. JEDEC Council Minutes from May 18- , 1992 state that a "discussion was held concerning patent policy. The Secretary outlined the genesis for changes and the fact that a new set of policy statements and guidelines have been written that wil be circulated to Council for review and comment. " (CX 35 at 9). 108 733. "Consensus was expressed that more strength is needed in our policy, however under existing laws, it seemed diffcult to do. This item wil be discussed further in the revision of 21- " according to the minutes of the January 19- , 1993 JEDEC Council meeting. (CX 46 at 9). 734. Some members wanted to redefine the patent policy to include patent applications and the intent to file patent applications. "Consensus was expressed that more strength is needed in our policy" was understood by JC 42. 3 Chair G. Kelley to mean "the more strength concept to be the inclusion of patent applications and material that might become patents to the concept patent requirements within the previous document. " (G. Kelley, Tr. 2421). 735. Existing EIA policy, which controlled JEDEC policy, did not permt such an expansive definition. "However, under existing laws, it seemed diffcult to do" was interpreted by JC 42. 3 Chair G. Kelley as follows: " (i)n my understanding, the diffculty was that the EIA Legal Guides did not include the patent application and material that might become patents concept, and the question before council was could we expand the definition under JEDEC Council control without endangering our position under the EIA control." (G. Kelley, Tr. 2422). 736. This helps explain why the possible solutions on intellectual property were never implemented. (See CX 13 at 32). 737. Instead of explicitly and formally changing the JEDEC policy from the EIA policy, the Council unsuccessfully attempted to redefine the word "patent. " JC 42. 3 Chair G. Kelley stated that "(a)t the JEDEC council, which was struggling with the change in wording of the JEDEC policy, we discussed the confict between the EIA wording of their patent policy and the change that we were making, which was patents and patent applications, and we believed as a group that the concept of patents includes patent applications, that the concept of patents is a concept which says avoid patents or material that could become patents, and if you can t avoid them, then you must deal with the RA requirements." (G. Kelley, Tr. 2696). 738. This attempted redefinition of the policy marked a departure both from established JEDEC policy and from EIA patent policy and caused confsion by creating ambiguity in the policy. (See F. 606- , 718-47). 739. Toshiba representative and JEDEC JC 42 Chairman Jim Townsend led the unsuccessful attempt to redefine JEDEC' s patent policy. Townsend was described as "a general with a flagpole patent" (G. Kelley, Tr. 2401-02), as "very sensitized by the WANG case (Sussman, Tr. 1353), and as someone on "a personal crusade." (CX 2079 at 38 (Karp Micron Dep. )). Townsend and the rest of the board wanted to ensure that Wang never happened again so that "the industry was not held hostage again. " (Willams, Tr. 786-87). 109 Changes in Policy Language EIA Patent Policy 740. Between 1991 and 1996, JEDEC "was an activity within the EIA engineering department" (1. Kelly, Tr. 2075) also described as "until early 2000, JEDEC was part ofthe EIA corporate structure. (1. Kelly, Tr. 1915). "Ifthere was a confict, the broader rules ofEIA would govern. (1. Kelly, Tr. 1916). 1. Kelly testified that in the event of a confict, any JEDEC manual would be subordinate to the EIA manuals. (1. Kelly, Tr. 1915-6). 741. Gordon Kelley, who was the chair of the JEDEC Council and of the JC 42. subcommttee during much of the relevant time, testified that he understood there to be a basic confict between the JEDEC and EIA manuals, for the EIA manuals intended the word "patents to mean simply "patents " while the JEDEC manual (at least by 1993) allegedly intended the word patents" to mean "patents and patent applications. " (G. Kelley, Tr. 2686-87; 2695-97). Up until late 1996, G. Kelley understood that EIA's definition of " patent" had not changed. (G. Kelley, Tr. 2697). 742. This contradicted testimony by EIA General Counsel John Kelly that EIA rules and JEDEC rules concernng disclosure and licensing of patents were consistent. (1. Kelly, Tr. 1915- , 1919-20). 1. Kelly testified that he believes that EIA's interpretation has always been that the term "patents" as used within EIA and JEDEC includes patent applications. (1. Kelly, Tr. 1887). 743. JEDEC manuals regarding the patent policy consistently refer the reader to the EIA . Legal Guides and both JEP 21-H and JEP 21-I state that EIA Legal Guides are controllng. Nothing in the EIA Guides indicates that patents refers to anything other than issued patents. (F. 633-38). Changes Found in JEP 21- 744. Both Gordon Kelley and John Kelly testified that the textual change in the 21- manual to include a reference to pending patents "was a restatement ofthe patent policy, and it in no way varied the policy itself" (1. Kelly, Tr. 1925; see also G. Kelley, Tr. 2415- 16). 745. However, G. Kelley contradicted his own testimony regarding whether 21- represented a change in policy, stating that in January of 1992 , " (t)he council was dealing with this revision of21- , and some major changes were going to be taking place in the commttees as a result of this revision." He indicated that the changes included "the inclusion of patent applications in the wording of the patent section. " (G. Kelley, Tr. 2411). G. Kelley later explained that the expanded wording "did not change the substance of the practice that we had been performing to this point, it just brought this document up to date to that practice." (G. Kelley, Tr. 2423). Later he explained , " (w)e were including the words in this document which added the requirement of disclosing patent applications to the document as we had been 110 practicing in JC-42 for several years at this point." (G. Kelley, Tr. 2431). 746. G. Kelley explained this contradiction as based on the ambiguous definition of the word "patent." When initially asked about his understanding in 1993 of the EIA patent policy as it related to patent applications, G. Kelley stated: " (t)he reason I'm struggling is that I understood after the beginnng of 1991 that the concept of patent included material that might become published patents and that changing the document (ie 21- I) to include patent applications was just a clarification but not a change in the policy, whether it was JEDEC, EIA or ANSI." (G. Kelley, Tr. 2679). He explained "what happened with me is my definition of ' patents changed. ... (TJhe patent policy in the JEDEC manuals, EIA manuals and ANSI manuals only specified ' patents,' which in my mind before 1991 meant issued patents. However, beginnng in early 1991 , it was very clear on the commttee that the commttee considered the issue of patents to be issued patents as well as material that might become issued patents." (G. Kelley, Tr. 2694- 95). 747. According to JEDEC Chairman Rhoden, the footnote in JEP 21-I which states that the word ' patented' also includes items and processes for which a patent has been applied and may be pending" was "added to further emphasize for anyone reading the document and to myself the word ' patent' has always applied to all things within the patent process inside of JEDEC , and that's the explanation that has always been given by myself inside of JEDEC commttees, and the footnote was added to add - make sure that everyone understood the word ' patent' involved everyhing within the patent process." (Roden, Tr. 316- 17). Conflcts in the Trial Testimony 748. The EINJEDEC patent policy cannot be based upon a common understanding of the policy, as the conficts in the trial testimony show that there was no common understanding. JEDEC members testified not only to different understandings of the policy, but some witnesses testimony was not credible and even contradicted their own prior testimony. (See F. 749-65). Trial Testimony Conflcts Regarding Whether the Patent Policy Applied to Patent Applications and Intentions to File Patent Applications 749. There was conficting testimony from JEDEC members regarding whether the patent policy applied to patent applications and intentions to file patent applications. One opinion that was expressed was that the word patents includes patent applications. (Calvin, Tr. 1006-07; 1. Kelly, Tr. 1886- , 1896-97; Landgraf, Tr. 1695-96; Lee, Tr. 6595-96; Willams, Tr. 771 , 909- 11). 750. Another opinion was that the policy extended to include an intent to file a patent application. For example, JC 42. 3 Chair G. Kelley testified that when JC 42 Chairman Townsend used the term "patents " " I understood him to mean an issued patent that was available from the 111 patent offce, patent applications that were being worked on with the patent offce, and items that were probably going to become patents. " (G. Kelley, Tr. 2406-07). 751. JEDEC Chairman Rhoden testified that in his "understanding of the policy, the term patent' applies to the patent process , anything in that patent process." (Rhoden, Tr. 636-38). Rhoden was unable to cite a JEDEC or EIA manual that expressly stated that disclosure had to be made of an intention to file a patent application, explaining that "I have seen in those manuals the wording that would say that it is a requirement for patents, and then it would be my interpretation of that that - operating in the commttee and in the guise of standardization that that would be covered and would be included. " (Rhoden, Tr. 639-40). 752. Moreover, there was testimony that presenters were required to disclose intellectual property before they advocated a particular technology which implies that non-presenting members were not under the same obligation. (See McGrath, Tr. 9273-74). For example, Intel representative Calvin testified: The reason I alluded to two different periods, and I can t tell you specific dates, is that I was aware initially that there was a policy that any applicable patents that might have effect on standard or development should be disclosed. I was also aware during that early period, and I don t know whether it was ' 92 or ' , but I was aware that the primary obligation was upon the presenting advocate of the standard, but that the secondary obligation, or almost to the same extent, I shouldn t say almost, it was to the same extent, was to anyone within the body that knew of patents that might have effect upon the standard. (Calvin, Tr. 1004. Trial Testimony Conflcts Regarding Whether Members Should Disclose Actual Claims or Whether a Patent Number Was Suffcient 753. There was a confict in the trial testimony regarding what should be disclosed under the policy. For example, one view was that the patent policy required a participant to disclose suffcient information to put the commttee on notice as to the nature of the relationship between the proposed standard and the intellectual property that might relate to the proposed standard. (1. Kelly, Tr. 1870-71; Calvin, Tr. 1010- 12; Rhoden, Tr. 627; Willams, Tr. 771- , 774- , 793- 94). 754. In contrast, other JEDEC members, including Board Chairman Desi Rhoden testified that it would be suffcient for a member simply to state that it "might have IP relating" to its presentation. (Roden, Tr. 1304-05). 112 755. IC 42. 3 Chair G. Kelley testified at trial to a disclosure obligation in direct contradiction to his own prior testimony. At the hearing, he testified that upon disclosure, a company must "describe the claims of the patent, probably paraphrased, sometimes handed out as a handout the published patent but more often paraphrased so that the commttee understood why the issues ofthat patent material applied to the discussion in JEDEC" and specifically stated that disclosure of a patent number alone was not enough. (G. Kelley, Tr. 2697-98). However, when asked, in reference to his own prior testimony in a Micron transcript , " (d)id you testify that you believed the giving of the patent number would be enough and that that would give you the information that you needed to go back and research the details on the patent?" he responded (t)he patent number would be enough. " (G. Kelley, Tr. 2700). Trial Testimony Conflcts Regarding Whether More Than Essential Patents Were Included in the Policy 756. There was conficting testimony regarding what should trigger disclosure. For example IC 42. 3 Chair and IBM representative Gordon Kelley testified that disclosure was triggered by a patent claim that "reads on or applies" to the standard, meaning that "if you exercise the design or production of the component that was being standardized (it) would require use of the patent. " (G. Kelley, Tr. 2706-07). 757. Another IBM JEDEC representative, Mark Kellogg, testified that his understanding was that "you have to disclose intellectual property that reads on the standard. " (Kellogg, Tr. 5311). Kellogg also stated that " (s)ometimes we disclose intellectual property that doesn (read on the standard) and one would question why. It adds confsion." (Kellogg, Tr. 5311). 758. Another opinion was that the EIA/JEDEC patent policy extended to patents and patent applications that "might be involved" in the standards under development. (CX 208A at 19 obligation of all participants to inform the meeting of any knowledge they may have of any patents, or pending patents, that might be involved in the work they are undertaking ); G. Kelley, Tr. 2705 ("there were many work items that occurred on the commttee that did not become standards. . . My definition says that any claim that might apply to the work of the commttee it was required to disclose. ); Landgraf, Tr. 1693-94 (disclose patents or applications "that would potentially be impacting the standard or proposed standard. ); Lee, Tr. 6595-96; Rhoden, Tr. 307; Sussman, Tr. 1346 (participants must disclose where there is a "gray" area); CX 2057 at 203-04 (Meyer, Dep. ) (disclosed patent when "suffciently close" to work of JEDEC); Willams Tr. 910- 11 (if "there would be a reasonable possibility that the patent was going to be associated with the work of JEDEC, that you ought to say, hey, I've got something I'm patenting here or there s something that you re talking about that I've got some IF on. )). 759. Yet another opinion was that the policy applies "if the intellectual property has any relevance to the work that's going on , it might be involved - we re not asking the people that are 113 disclosing to actually try to do a determnation of whether it applies or doesn t apply. We saying ifit's related , in the same general area , . . . " (Rhoden, Tr. 322-23). 760. This confict in trial testimony highlights the ambiguity of the JEDEC policy. (F. 718-39). Trial Testimony Conflcts Regarding the Timing of Disclosure 761. Consistent with the EIA patent policy which encourages disclosure of essential patents, early disclosure was encouraged at JEDEC. (1. Kelly, Tr. 1955-56; Willams, Tr. 772; 910- 11). 762. Some members understood this to mean that disclosure was expected " (i)fthere is any suggestion that the committee s work should move in a certain direction." (Wiliams, Tr. 1984). 763. Another opinion was that any obligation that may have existed was not triggered until the time that a proposal was balloted for approval. (G. Kelley, Tr. 2707). IC 42. 3 Chair G. Kelley testified " (t)he policy at JEDEC was that the disclosure should occur as soon as possible in the discussion of the material and certainly by the time it was balloted." (G. Kelley, Tr. 2702; see also CX 2057 at 211 (Meyer, Dep. ) (testimony by Siemens JEDEC representative Wili Meyer that although it was "good practice" to notify the commttee before balloting, "the ballot was considered the deadline when it should have been done )). 764. Cray representative Grossmeier, although he testified that "if a patent holder has a patent that in any way was applicable to a proposed standard, they were to disclose that at the time of balloting within the commttee " pointed out that " (t)here s probably thousands of patents that are applicable to every device that s built, basically semiconductor technology patents that undoubtably are being duplicated by other companies. You can t disclose every - I mean, there would be lists of thousands of patents on every standard. " (Grossmeier, Tr. 10945 , 10956). 765. Yet another opinion was that disclosure was not tied to any procedural formality in the JEDEC process. (1. Kelly, Tr. 1983-85; Rhoden, Tr. 488-89). The Scope of the EWJEDEC Patent Policy Disclosures Were Encouraged and Voluntary 766. The controllng EIA manuals do not refer to or impose a mandatory obligation to disclose intellectual property. (See CX 204 at 4; CX 203A at 11; JX 54 at 9- 10; see supra 633-38). 114 767. JEDEC manuals also do not impose any mandatory disclosure duty. JEP 21- , in effect when Rambus joined JEDEC, states that "JEDEC standards are adopted without regard to whether or not their adoption may involve patents" and does not provide any further guidance regarding intellectual property. (CX 205 at 20; see supra F. 606-32). JEP 21-1 refers to, but does not impose, an obligation to disclose intellectual property. (CX 208 at 19 26; see supra 610-32). 768. The commttee forms including the membership application, sign-in/attendance roster, commttee ballot, members' manual , and patent tracking list do not refer to or impose an obligation to disclose intellectual property, although the commttee ballot requests those aware of patents involved in the ballot to "please" alert the commttee. (CX 601 at 1-2; CX 306 at 1-2; CX 252A at 2; RX 507 at 15; see supra 646-69). 769. The contemporaneous correspondence also shows that disclosure was voluntary. (RX 669 at 3 (EIA, on behalf of JEDEC, told the FTC in a January 22, 1996 letter that it encourage(s) the early, voluntary disclosure of patents that relate to the standards in work." RX 742 at 1 (statement in JEDEC Secretary s 7/10/96 memorandum to JEDEC Council members that the EIA "encourage(s) early voluntary disclosure of any known essential patents ); RX 1585 at 1 (statement in JEDEC Secretary s 2/11/00 email that " (d)isclosure of patents is a very big issue for Commttee members and cannot be required of members at meetings )). 770. Moreover, there is no evidence that any JEDEC member objected when Gordon Kelley of IBM and Hans Wiggers of Hewlett-Packard announced at JEDEC meetings that they would not be disclosing any intellectual property tfom their companies. (JX 15 at 6; RX 420 at 2; JX 18 at 8; Wiggers, Tr. 10592-94; see supra F. 691-700). 771. Complaint Counsel did not provide suffcient evidence tfom which to find that the EIA/JEDEC patent policy in effect while Rambus was a member did anything more than encourage the disclosure of patents essential to the standards at balloting. Patent Applications or Intentions To File Patent Applications Were Not Covered by the Policy 772. The controllng EIA manuals refer to "patents " " known patents " and "patented item or process " but never refer to patent applications. (See, e. CX 204 at 4; CX 203A at 11; JX 54 at 9- 10; see supra F. 633-38). In addition, there was testimony tfom G. Kelley that EIA' definition of the word "patent" did not include patent applications. (G. Kelley, Tr. 2686-87; 2695-97). 773. The contemporaneous documents show that the JEDEC patent policy encouraged the disclosure of patents, not patent applications or intentions to file patent applications. The minutes of the February 2000 meeting of the JEDEC Board of Directors state that disclosure patent applications is "not required under JEDEC bylaws." (R 1570 at 13). A few days after 115 the meeting, JEDEC Secretary Ken McGhee explained to the members of JEDEC 42.4 that the disclosure of patent applications went "one step beyond" the policy and that even disclosure of patents could not be required: "Disclosure of patents is a very big issue for Commttee members and cannot be required of members at meetings." (R 1582 at 1). 774. The most that the record evidence can be understood to support is an argument that presenters were expected to disclose patent applications that related to technologies they were asking that JEDEC standardize. (R 507 at 15; McGrath, Tr. 9273-74). Members Were Encouraged To Disclose Patents That Were Essential To Practice the Standard 775. Disclosure was only encouraged of patents that were "essential" to a standard, i. those patents that were necessary for the manufacture or use of a product that complied with the standard. (CX 203A at 11 (standards that "call for the use of patented items); JX 54 at 9 (standards "that call for the exclusive use of a patented item or process ); CX 208 at 19 (standards that "require the use of patented items ); RX 742 at 1 ("known essential patents )). 776. Hewlett-Packard representative Thomas Landgraf testified that he understood the patent policy to involve disclosure if "the standard required someone else s idea to be used. . . in order for it to operate. " (Landgraf, Tr. 1695). 777. JC 42. 3 Chair and IBM representative Gordon Kelley testified that the disclosure duty was triggered by a patent claim that "reads on or applies" to the standard, meaning that " you exercise the design or production of the component that was being standardized (it) would require use of the patent. " (G. Kelley, Tr. 2706-07). 778. Another IBM JEDEC representative, Mark Kellogg, testified that his understanding was that "you have to disclose intellectual property that reads on the standard. " (Kellogg, Tr. 5311). Kellogg also stated that " (s)ometimes we disclose intellectual property that doesn (read on the standard) and one would question why. It adds confsion. " (Kellogg, Tr. 5311). There Was No Duty To Search for Intellectual Propert Issues 779. It was undisputed at trial that JEDEC representatives had no obligation to do any investigation, research or inquiry of their own company or its lawyers regarding possible intellectual property interests relating to JEDEC work. (Rhoden, Tr. 623-24; G. Kelley, Tr. 2451 2700-01; 1. Kelly, Tr. 1966-68; CX 2057 at 189, 193 (Meyer, Dep. ); see also RX 1712 at 8 (no duty to search under ANSI Guidelines)). 116 The Policy was Limited To Participants With Actual Knowledge 780. The patent policy applied only to people with "actual knowledge." (Roden, Tr. 623-24). JEDEC Board Chairman Desi Rhoden testified that the disclosure obligations under the JEDEC patent policy were "triggered by the actual knowledge of the people that were involved and that would not be just the representative at the meeting, but all of the people that would have been involved in . . . The knowledge of the people that are involved in the process." (Roden Tr. 624; 1. Kelly, Tr. 1970). 781. Rambus s JEDEC representative, Richard Crisp, testified that during the time that Rambus was a JEDEC member, he: (1) had not seen any Rambus patent application with claims over an SDRA that used any of the four features at issue here; and (2) did not know one way or the other whether Rambus s pending patent applications covered JEDEC-compliant SDRAs using any of those features. (Crisp, Tr. 3540-43; 3461-66). The Patent Policy Did Not Apply After a Company Withdrew From JEDEC 782. Afer a company left JEDEC it had no obligations under the patent policy. (See Kelley, Tr. 2700-01). If Disclosure Was Made, It Was Encouraged No Later Than the Time of Balloting 783. Consistent with EIA patent policy to encourage early disclosure of relevant patents early disclosure was encouraged at JEDEC. (1. Kelly, Tr. 1955-56; Wiliams, Tr. 772 910- 11). 784. The commttee ballot was considered the deadline for disclosure. (G. Kelley, Tr. 2707; Grossmeier, Tr. 10945). JC 42. 3 Chair G. Kelley testified "(t)he policy at JEDEC was that the disclosure should occur as soon as possible in the discussion of the material and certainly by the time it was balloted. " (G. Kelley, Tr. 2702; CX 2057 at 211 (Meyer, Dep.) (testimony by Siemens JEDEC representative Wili Meyer that although it was "good practice" to notify the commttee before balloting, "the ballot was considered the deadline when it should have been done )). 785. This is consistent with the patent tracking list which asked the commttee chair to resolve patent status prior to ( choose one)," followed by a list of events, tfom presentation to balloting. (CX 34 at 7; CX 711 at 169; JX 27 at 7-8; JX 28 at 15- 18). 117 VI. JEDEC 42.3 COMMITTEE MEMBERS WERE NOT MISLED BY RAMBUS ON ISSUES RELATING TO RAMBUS INTELLECTUAL PROPERTY JEDEC Committee Leaders and Members Were Fully Aware of Rambus Patents With Respect To Features Being Considered for Incorporation into JEDEC Standards Crisp Did Not Mislead JEDEC At the May 1992 Committee Meeting Regarding Rambus s Intent To Seek Patent Rights Over Certain SDRAM Features ffM and Siemens 786. In the spring of 1992, IBM and Siemens (whose former semiconductor division is now called Infneon Technologies) were cooperating on a joint venture to develop and produce a new DRA design. (G. Kelley, Tr. 2532; CX 2088 at 277- 310 (Meyer, Infneon Trial Tr.)). 787. Both the Siemens JEDEC representative, Wili Meyer, and the IBM JEDEC representative, Gordon Kelley, were involved in the Siemens/IM DRA development efforts in the spring of 1992. (G. Kelley, Tr. 2620-21). The efforts included a consideration of the Rambus technology. (G. Kelley, Tr. 2627). 788. In March 1992, G. Kelley prepared a memorandum regarding Rambus. (RX 240 at 1). G. Kelley s March 19, 1992 memorandum refers to "unique (and probably patented) Rambus protocol" and "special Microprocessor and DRA interface (other than industry standard). (R 240 at 1). G. Kelley s memorandum also states that he had asked an IBM in-house lawyer to get me a copy of Ram bus patents." (RX 240 at 1). 789. On April 23 , 1992, G. Kelley attended a presentation at IBM by Rambus founder Mike Farmwald and Rambus executive David Mooring. (G. Kelley, Tr. 2631; RX 273 at 1). 790. According to handwritten notes of the April 23 , 1992 Rambus/IM meeting a Rambus representative stated at the meeting that Rambus intended to obtain "license fee + royalties tfom IC company. " (CX 2355 at 1). The notes also state that Rambus "want(s) to set industry std." (CX 2355 at 1). 791. In April 1992, Gordon Kelley prepared a "Rambus Assessment" along with two other IBM employees, Dr. Beilstein and Michael Clinton. (RX 279 at 1). The "Rambus Assessment" is dated April 24, 1992, the day after Kelley had attended the presentation by Rambus. (R 279 at 1; G. Kelley, Tr. at 2635). 792. The April 1992 "Rambus Assessment" that G. Kelley co-authored refers to "Unique Rambus Features/Attributes." (R 279 at 1). The "Rambus Assessment" also states that "Intel is 118 Rambus licensee" and notes a "potential future Intel memory strategy to marry. . . 586/686 processor with Rambus protocol to corner PC/notebook market with state of the art performance." (RX 279 at 4). 793. The "Rambus Assessment" states that "Rambus can work techncally" and notes "the risk is whether it becomes a standard for the low end - bulk of DRA bit volume - and that it provides a simple low end solution for anyone to get into the PC business." (R 279 at 8). 794. The "Rambus Assessment" states that "(i)fRambus fails to become standard, then it is business as usual for BTV (the acronym for IBM' s Burlington, Vermont operations) and the SDRA has a significant chance of being standard." (R 279 at 7). 795. It is apparent tfom G. Kelley s March and April 1992 analyses of Ram bus that he was aware of Rambus technology, and its prospects for success in the spring of 1992. (See RX 279; RX 273; RX 240). 796. One week after G. Kelley finalized the April 24, 1992 "Rambus Assessment " he participated in a conference call with Siemens JEDEC representative Will Meyer. The call included a discussion of Ram bus. (R 286A at 1). 797. Meyer prepared an April 30, 1992 memorandum reflecting the conference call which states in part: "Rambus: Visited key in-house IBM users. IBM is stil keeping its eye on RAUS. RAUS has announced a claim against Samsung for USD 10 millon due to the similarity ofthe SDRAwith the RAUS storage device architecture. For that reason, IBM is seriously considering to preemptively obtain a license as soon as possible (at an introductory price)." (R 286A at 2; CX 2088 at 317- 19 (Meyer, Infneon Trial Tr.)). 798. Meyer testified that during the conference call, Gordon Kelley had provided the Rambus-related information contained in Meyer s April 30, 1992 memorandum. (RX 286A; CX 2088 at 317- 19 (Meyer, Infneon Trial Tr. )). 799. Siemens executive Martin Peisl similarly testified that the information regarding Rambus that is contained in Meyer s April 30, 1992 memorandum "seems to be information coming tfom IBM or Gordon Kelley. " (Peisl, Tr. 4517). 800. G. Kelley and Meyer were both aware, as of April 30, 1992, of a possibility that Rambus might assert some intellectual property claims "due to the similarity of the SDRA with the RAUS storage device architecture." (R 286A at 2). 801. An April 16, 1992 IBM memorandum referenced the fact that an-in house lawyer, 1. Walter, had been asked to review and comment upon Rambus related intellectual property issues. (RX 272 at 2). 119 802. Meyer also wrote a separate memorandum dated April 30, 1992 that stated in part that " (t)he original idea behind the SDRA is based on the basic principle of a simple pulse input (IBM toggle pin) and the complex RAUS structure." (R 285A at 5). This memorandum also demonstrates Meyer s awareness of similarities between the SDRA device and the RAUS structure. (See RX 285A at 5). 803. On May 6, 1992, Meyer prepared a char showing the "Pros" and "Cons" of "Sync DRA " " Rambus DRA " and "Cached DRA." (R 289 at 1). 804. In his May 6, 1992 "Pros" and "Cons" chart, Meyer stated that the " bank" synchronous DRA "may fall under Rambus patents." (R 289 at 1). Meyer testified that he did not think Rambus had patents at the time covering 2-bank synchronous DRA but that there was the potential it could obtain such patents. (CX 2089 at 44 (Meyer, Infneon Trial Tr.)). 805. Meyer testified that at the time, he thought there was a potential that Rambus would obtain patents covering two-bank features that may be included in SDRAs. (CX 2089 at 44 (Meyer, Infneon Trial Tr.)). 806. Meyer also testified that in 1992 , " we were absolutely sure that Rambus was trying to get patents." (CX 2088 at 75 (Meyer, Infneon Trial Tr.)). The May 1992 JC 42.3 Meeting 807. On May 7, 1992, Meyer and G. Kelley attended a JC 42. 3 subcommttee meeting in New Orleans, Louisiana. (CX 34). 808. The May 1992 meeting was Richard Crisp s first formal JC 42. 3 subcommttee meeting as Rambus s JEDEC representative, (CX 34 at 1; Crisp, Tr. 2929), although he had attended a JC 42. 3 task group meeting on April 9 and 10, 1992. (Crisp, Tr. 3009- 10). 809. At the meeting, Gordon Kelley asked Crisp if he would like to comment on whether Rambus had patents or potential patents covering two bank design. Crisp declined to comment. (CX 673 at 1; CX 2089 at 136-37 (Meyer, Infneon Trial Tr. )). 810. Howard Sussman ofNEC commented to the group that he had seen a copy of a Rambus s foreign patent application. (CX 2092 at 128 (Crisp, Infneon Trial Tr. )). According to Crisp, the essence of the comment was that Sussman had obtained a copy of the application tfom the foreign patent offce, had read it and concluded that it should not be a concern for the JEDEC standardization effort because, according to Sussman , " many, many claims. . . are anticipated by prior ar. " (CX 673 at 1). 811. The witnesses who testified about the May 1992 exchange between G. Kelley and Crisp were Kelley, Crisp, Siemens representative Wili Meyer, IBM representative Mark Kellogg 120 and Intel representative Samuel Calvin. (G. Kelley, Tr. 2662; Crisp, Tr. 3066; Kellogg, Tr. 5055- 56; Calvin, Tr. 1066-69; CX 2089 at 169, 136 (Meyer, Infneon Trial Tr. )). 812. Calvin, the Intel representative, testified that he recalls that at the JEDEC meeting, Crisp was asked if he cared to comment about whether Rambus had patents or intellectual property that covered a particular subject. (Calvin, Tr. 1068-69). Calvin recalls that Crisp declined to comment. (Calvin, Tr. 1068-70). 813. Meyer, who was Siemens s primary JEDEC representative between 1992 and 1996 testified that at the May 1992 meeting, he asked G. Kelley to ask Crisp "whether (he) would like to comment" about whether Rambus had patents relating to the use of two banks in a DRA. (CX 2089 at 133-34 (Meyer, Infneon Trial Tr.); CX 2057 at 66 (Meyer, Infneon Dep. )). 814. Meyer testified that "(t)he way how Kelley formulated the question was: Do you want to give a comment on this?" (CX 2088 at 136, 164 (Meyer, Infneon Trial Tr.)). Meyer testified that Crisp "just shook his head. " (CX 2088 at 136, 164 (Meyer, Infneon Trial Tr.)). 815. Meyer s trip report of the May 1992 meeting states in part: "Siemens and Philips concerned about patent situation with regard to Rambus and Motorola. No comments given. (R 297 at 5). 816. Crisp sent an email on May 6, 1992 that described his exchange with Kelley in this manner: " Siemens expressed concern over potential Rambus Patents covering designs. Gordon Kelley of IBM asked me if we would comment which I declined. " (CX 673 at 1). 817. Gordon Kelley testified that Siemens representative Wili Meyer had raised an "issue of concern with Rambus and Rambus patents" at the May 1992 meeting. (G. Kelley, Tr. 2662). Kelley recalls that Meyer had asked Crisp if he knew whether Rambus "had patentable material on the concept ofthe synchronous DRA." (G. Kelley, Tr. 2543). Kelley recalls that Crisp declined to comment in response to that question. (G. Kelley, Tr. 2662). 818. G. Kelley testified that he could not recall whether he had said anything at the May 1992 JEDEC meeting about possible Rambus patent claims. (G. Kelley, Tr. 2544). 819. G. Kelley also testified that a "no comment" tfom a JEDEC member in response to a question about intellectual property is "unusual" and "surprising" and "is notification to the commttee that there should be a concern. . . . " (G. Kelley, Tr. 2579). 820. IBM representative Mark Kellogg prepared contemporaneous handwritten notes at the May 1992 JEDEC meeting that refer to the concerns Meyer had raised. (R 290 at 3). Kellogg s notes state: " Siemens: Kernel of chip similar to Rambus. Patent concerns? (No Rambus comments)." (R 290 at 3). 121 821. Kellogg testified that when he used the phrase "kernel of the chip" in his notes, he was referring to Meyer s concern that "the fundamental architecture of the SDRA device" was similar to Rambus. " (Kellogg, Tr. 5324). 822. Kellogg testified that he took his notes at the May 1992 meeting in part to act as " log of events" and "also to initiate action on my part or the part of others." He said that this discussion "would have been a flag, which is why I wrote it down. " (Kellogg, Tr. 5322). 823. Kellogg testified that he considered the discussion a "flag" because JEDEC members were "describing possible intellectual property concerns which may affect our decision process for synchronous DRA." He testified that " (t)hat is a concern" and that " (t)he lack of response by Rambus is also a concern." (Kellogg, Tr. 5323). 824. The chairman of the meeting, Gordon Kelley, testified that prior to the May 1992 meeting Crisp had spoken to him about the possibility of Ram bus scheduling a presentation concerning DRA design. (G. Kelley, Tr. 2553). G. Kelley also testified that he had refused to allow Rambus to present its technology for standardization at JEDEC on this and another occasion, even though he had never barred any other member company tfom presenting its technology. (G. Kelley, Tr. 2649-58). 825. G. Kelley had a clear confict of interest; he made and enforced his unilateral decision to bar Rambus tfom presenting its technology two weeks after he wrote in an internal company document that his company s interests were threatened by the Rambus technology and were best served ifRambus "fails to become standard." (R 279 at 7). He did not disclose this confict to Crisp or to anyone else. (G. Kelley, Tr. 2656-57). PCT Application 826. A "PCT" application is an international patent application filed pursuant to the Patent Cooperation Treaty. (CX 1454 at 1). Rambus had filed a PCT application on April 16 1991 that was identical in all material respects to the ' 898 application it had filed at the same time in the U.S. (Fliesler, Tr. 8811; see CX 1451; CX 1454). 827. Pursuant to the procedures governing applications filed under the Patent Cooperation Treaty, Rambus' s PCT application became publicly available as of October 31 , 1991. (CX 1454 at 1; First Set of Stipulations, Stip. 8). 828. NEC' s Sussman testified that he did not find anything in the PCT application that related to the work ongoing at JEDEC." (Sussman, Tr. 1445). 122 After the May 1992 JC-42.3 Meeting 829. Roughly one week afer the May 1992 meeting, Siemens s JEDEC representative Wili Meyer also reported that: "Siemens and Philips: concerned about patent situation with regard to RAUS and MOTOROLA. No comments given. Motorola patents have priority over RAUS' . RAUS patents filed but pending." (RX 297 at 5). 830. In June 1992, G. Kelley gave a presentation about Rambus to a group of about 30 engineers. Half ofthe engineers were tfom IBM; half were tfom Siemens. (G. Kelley, Tr. 2658- 59). 831. In connection with his June 1992 presentation, G. Kelley prepared a char entitled COMPAR ALTERNATIVES for Future High Performance, High Volume DRA Designs. The chart listed "Pros" and "Cons" of Sync DRAs and Rambus DRAs. One ofthe two cons" listed for Sync DRAs was "Patent Problems? (Motorola/ambus)." (R 303 at 1; G. Kelley, Tr. 2545). 832. Kelley testified that he included the reference to possible "patent problems involving Motorola and Rambus in his June 1992 "Pros" and "Cons" chart because he "was notifying the people involved in the design of the joint work that was going on between IBM and Siemens that there was concern about potential patent problems as I had heard at the JEDEC meeting about Motorola and Rambus intellectual property, and I wanted the group to recognize that there was this concern. " (G. Kelley, Tr. 2545). 833. Meyer testified that in September 1992 he had prepared a presentation entitled What Is Rambus?" (RX 321 at 1; CX 2089 at 66-67 (Meyer Infneon Trial Tr.)). Meyer delivered this presentation to, among others, Dr. Schumacher, the current CEO ofInfneon. (CX 2089 at 66-67 (Meyer, Infneon Trial Tr. )). 834. In his September 1992 presentation, Meyer referred to Rambus as a "deadly menace to the established computer industry." (R 321 at 2). He also suggested that to "protect" the computer industry, someone could "buy Rambus and dump it." (RX 321 at 3). Meyer testified that he thought some of his competitors were so worried about Rambus that they might purchase the entire company and "bury the technology." (CX 2089 at 89 (Meyer Infneon Trial Tr. )). 835. G. Kelley testified, in a 2001 deposition, that he had had conversations with Meyer after 1992 regarding the potential applicability of Ram bus patents to SDRA devices. At trial he could not recall the substance of these conversations. (G. Kelley, Tr. 2664-65). 123 PCT Application Discussed At the September 1993 Meeting 836. At the September 1993 meeting Crisp disclosed to the Commttee the issuance to Rambus on September 7 1993 , of United States Patent No. 5 243 703. (Crisp, Tr. 3173; First Set of Stipulations, Stip. 11). 837. The ' 703 patent was the first Rambus patent and had issued shortly before the meeting. The ' 703 patent resulted tfom a divisional application of an original application, Serial No. 07/510 898 ('898 application), filed in April 1990. (First Set of Stipulations, Stip. 11). 838. The specification and drawings ofthe ' 703 patent are substantially the same as those contained in the ' 898 application. (Fliesler, Tr. 8812, 8817; see RX 425 at 1; CX 1451 at 1). 839. There was an additional discussion ofRambus s PCT application at a JEDEC meeting in September 1993 , after Rambus representative Richard Crisp disclosed that Rambus had obtained its first U.S. patent (the ' 703 patent). According to Siemens s JEDEC representative Will Meyer: During the meeting, which was the same meeting in which the Rambus ' 703 patent was disclosed with its full patent number, and a participant, I'm not quite sure , either the participant or the chairman or the JEDEC offcial, somebody at the meeting said by the way, there is also something called like a WIO, World Intellectual Property, and he offered to anybody who was interested in it to get the number tfom him, the reference number, and to step up to him after the meeting to do so. (CX 2058 at 298 (Meyer, Infneon Dep. )). 840. Meyer also testified that he obtained the serial number for Rambus s WIO application at the JEDEC meeting and "sent it back to the (Siemens) patent department." (CX 2089 at 112 (Meyer, Infneon Trial Tr. )). 841. A few months later, in March 1994, Meyer prepared a memorandum about Rambus for a Siemens engineering manager named Penzel. The memorandum stated in part that "(a)ll computers wil (have to be) built like this some day, but hopefully without royalties to RAUS." (R 488A at 1; CX 2089 at 124 (Meyer, Infneon Trial Tr.)). The May 1995 JC 42.3 Meeting 842. At the May 24, 1995 JEDEC meeting, presentations were made by several JEDEC members regarding a "next generation" memory technology called "SyncLink. " (JX 26 at 10- 11). At this meeting there were a number of inquiries about possible patent issues pertaining to 124 SyncLink. G. Kelley of IBM asked whether or not HP, Hyundai, Mitsubishi or TI had any patents covering any of the matters being presented; all ofthese companies stated that they did not. (CX 711 at 72; Crisp, Tr. 3265-66). 843. At this same meeting, Sam Calvin of Intel and G. Kelley also inquired whether there were any Rambus patents covering the SyncLink technology. (CX 711 at 73; Crisp, Tr. 3266). When Crisp did not respond to this inquiry at the meeting he was asked by Kelley to go back to Rambus and then report back to the Commttee whether Rambus knew of any patents, especially Rambus patents, that may read on the SyncLink technology. (CX 711 at 73; CX 794 at 4; Crisp, Tr. 3267-68). 844. Crisp wrote an email informing the Rambus executives, engineering managers and business development and marketing groups of this development. In that email he listed a few ideas he had of Ram bus intellectual property relating to SyncLink. (CX 711 at 68, 73). He also suggested that Rambus review its current issued patents and see what it had to work against SyncLink. (CX 711 at 68, 73). He recommended that Rambus consider responding to the JEDEC request by "simply provid(ing) a list of patent numbers which have issued" and tellng members to decide for themselves what does and does not ininge. He added, however, that if the Rambus patents were "not a really key issue. . . Then it makes no sense to alert them to a potential problem they can easily work around " and that "we may not want to make it easy for all to figure out what we have especially if nothing looks really strong. " (CX 711 at 68, 73). 845. Rambus executives heeded Crisp s advice and Crisp testified at trial that at the September meeting, he made "no statement to the 42. 3 subcommttee that (he) believed that SyncLink would violate Rambus patents. " (Crisp, Tr. 3316). 846. A few days after the May 1995 meeting, Crisp sent an email to Reese Brown, a JEDEC consultant, that included a reference to "Ramlink " the foundation for the proposed SyncLink device. (CX 711 at 80-82; Gustavson, Tr. 9281-83). Crisp s email stated in part that he took exception to the fact that Brown had posted a copy ofthe ballot for the proposed IEEE Ramlink standard on the JEDEC reflector. (CX 711 at 76-78; Crisp, Tr. 3280-82). 847. When Brown responded to Crisp and suggested that Crisp s exception was partly due to the fact that Crisp saw the standard as competition to Rambus, Crisp responded that the proposed IEEE standard was not real and had patent issues associated with it. (CX 711 at 79-80; Crisp, Tr. 3282-83). Crisp admitted that he had not planned ahead oftime to disclose this but did it in the heat ofthe moment. (Crisp, Tr. 3282-83). 848. Brown forwarded Crisp s email to Hans Wiggers, the JEDEC representative for Hewlett-Packard, who was chairing the RamlinkSynclink working group. (CX 711 at 88-91; Gustavson, Tr. 9282-83). 125 849. On June 10, 1995 , Wiggers copied his response to Crisp s comments to, among others, Gordon Kelley, the Chairman of the JC 42. 3 subcommttee, along with a request that Crisp clarfy his comments about patents relating to Ramink. (CX 711 at 90-91). 850. On June 12, 1995, Kelley prepared an internal IBM memorandum that stated with respect to the SyncLink device that "the Rambus patents should be closely reviewed." (R 575 at 7). 851. On June 13 , 1995 , Crisp sent an email to Wiggers that stated: (R)egarding patents, I have stated to several persons that my personal opinion is that the RamlinkSynclink proposals wil have a number of problems with Rambus intellectual property. We were the first out there with high bandwidth, low pincount; DRAs, our founders were busily at work on their original concept before the first Ramlink meeting was held, and their work was documented dated and filed properly with the US patent offce. Much of what was filed has not yet issued, and I cannot comment on specifics as these filings are confdential. (RX 576 at 2). 852. Crisp s email to Wiggers also stated that: I was asked at the last JEDEC meeting to report on our patent coverage relative to SyncLink as proposed at JEDEC at the next meeting in Crystal City in September. Our attorneys are currently working on this, so I think I wil be in a position to make some sort of offcial statement at that time and plan to do so. In the meantime, I have nothing else to say to you or the rest of the commttee about our patent position. If you want to search for issued patents held by Rambus, then you may learn something about what we clearly have covered and what we do not. But I must caution you that there is a lot of material that is currently pending and we will not make any comment at all about it until it Issues. (R 576 at 2). 853. In August 1995, Rambus warned the SyncLink working group that its work might intinge Rambus s intellectual property. The minutes of the August 22, 1995 , meeting of the SyncLink working group state in part as follows: 126 Richard Crisp, ofRamBus, informed us that in their opinion both RamLink and SyncLink may violate RamBus patents that date back as far as 1989. Others commented that the RamLink work was public early enough to avoid problems, and thus might invalidate such patents to the same extent that they appear to be violated. However, the resolution of these questions is not a feasible task for this commttee, so it must continue with the techncal work at hand. (R 592 at 2). 854. Although the August 21 , 1995 SyncLink meeting was held under the auspices ofthe standards setting body IEEE, not JEDEC, each of the seven companies represented at the SyncLink meeting was also a JEDEC member company, and at least five of the engineers present at the SyncLink meeting were JEDEC representatives who attended the next JEDEC 42. meeting on September 11 , 1995. (See First Set of Stipulations, Stip. 21). The September 1995 JC 42.3 Meeting 855. At the September 1995 JEDEC meeting, Crisp presented a written response to the questions about intellectual property that had been raised at the May 1995 meeting. The statement included this passage: At this time, Rambus elects to not make a specific comment on our intellectual property position relative to the SyncLink proposal. Our presence or silence at commttee meetings does not constitute an endorsement of any proposal under the commttee consideration nor does it make any statement regarding potential intingement of Ram bus intellectual property. (JX 27 at 26). Rambus s statement was published in full in the offcial JEDEC minutes ofthe September 1995 meeting. (JX 27 at 26). 856. A September 1995 meeting report prepared by Motorola JEDEC representative Mark Farley noted that "Rambus made a non-statement statement to the commttee saying that Rambus has been developing this technology for five+ years and has a substantial number of patents related to high-bandwidth DRAs." (R 615 at 1). Farley also reported that " SyncLink told Motorola confdentially that there were very likely patents violated by their proposal." (R 615 at 1). 857. Intel representative Samuel Calvin testified that at that time, he understood tfom Rambus s September 11 , 1995 statement that any silence by Rambus at JEDEC meetings should not be taken as an indication that it did not have intellectual property relating to JEDEC' s work. (Calvin, Tr. 1070). 127 Rambus Met With Manufacturers and Suppliers 858. In the course of the discussion of the Rambus letter at the September 1995 Commttee meeting, Crisp reminded the Commttee that Rambus in the past had reported a Rambus patent to the Commttee, referring to the disclosure to the Commttee of the Rambus 703 patent in September 1993. (Crisp, Tr. 3312). Crisp "reminded them ofthe 14 patents relating to SDRAs, and that our silence was not an agreement that we have no IF related to SyncLink, . . . (and I) reminded them that the member companies are constantly receiving patents on things they are standardizing and that they seldom report the patents." (CX 711 at 167). 859. During a meeting in Korea in October 1995, Rambus informed LG Semiconductor that Rambus had or might obtain intellectual property rights that might apply to SDRAs. (CX 2111 at 315- 16 (Tate Dep. )). 860. During a meeting in Korea in October 1995, Rambus informed Samsung that SyncLink and fast SDRAs were heading in the direction where they might ininge future Rambus patents. (CX 2111 at 317 (Tate Dep. )). 861. During a meeting in Japan in October 1995, Rambus informed NEC that SyncLink and new SDRAs (SDRAs using a PLL or dual-edge clock) might end up in a position where they ininged future Rambus patents. (CX 2111 at 320-21 (Tate Dep. )). 862. During a meeting in Japan in October 1995, Rambus informed OK! of the possibility that there would be Rambus intellectual property that might apply to SyncLink and new SDRAs. (CX 2111 at 320-22 (Tate Dep. )). 863. During a meeting with Intel in October 1995, Rambus informed Intel that it did not see how future memory chips could meet performance goals without using some or all of Rambus s inventions. (CX 2111 at 323-26 (Tate Dep. )). 864. DRA manufacturer Micron Technology demonstrated its concern about Rambus patents in 1995 and 1996. On November 7, 1995, Micron executive Jeff Mailoux sent a memo entitled "RAUS Inc. patents" to several other Micron employees, including JEDEC representative Terry Walther. (R 630 at 1). Mailoux s memorandum stated in part as follows: (a)ttached are abstracts for the patents that have been granted to RAUS Inc. so far. . . . Please consider both the quality (is there prior art?) and the breadth (apply to more than just RAUS?) of the patents." (R 630 at 1). 865. Mitsubishi' s Japanese patent department was also apparently considering any prior art to Rambus s patents in November 1995. (R 1041A at 1 ("we have obtained CRAY Corporation s patents to investigate the prior art for the patents owned by Rambus Inc. . . . )). 128 866. In January 1996, the concerns of Micron and others about Rambus s intellectual property were reflected in the minutes of the SyncLink Consortium: "Rambus has 16 patents already, with more pending. Rambus says their patents may cover our SyncLink approach even though our method came out of early RamLink work. Micron is particularly concerned to avoid the Rambus patents, though all of us share this concern." (R 663 at 2). 867. Others who took a close look at Rambus s intellectual property in this time period included Dr. David Gustavson, the Secretary of the SyncLink Consortium, who reviewed several European patent applications that Rambus had filed. (Gustavson, Tr. 9286). Dr. Gustavson has testified that he recognized immediately upon reviewing the Rambus patent applications that they had a broad scope that would apply to virtually any memory device, but that he believed the applications would never be allowed in light of their breadth. (Gustavson, Tr. 9287). 868. Two Apple engineers, David James and Glen Stone, reviewed the Rambus patent applications along with Gustavson. (Gustavson, Tr. 9286). JEDEC Members Viewed Rambus s Patents As a Collection of Prior Art 869. Crisp s May 6, 1992 email states that: In response to the patent issue, Sussman stated that our patent application is available tfom foreign patent offces, that he has a copy, and noted many, many claims that we make that are anticipated by prior art. He also stated the Motorola patent predated ours (not the filing date!) and it too was anticipated by prior art. (CX 673 at 1). 870. The handwritten notes taken contemporaneously at the May 1992 meeting by IBM representative Mark Kellogg similarly indicate: "NEC: Rambus International Patent 150 pages Motorola patents/Rambus patent - suspect claims won t hold." (R 290 at 3). The Dell Consent Order and Rambus s Last JEDEC Meeting- December 1995 To January 1996 871. The final JEDEC meeting attended by Rambus was the meeting in December 1995. (CX 2104 at 853-54 (Crisp, Micron Dep. )). Rambus did not pay in response to a dues invoice sent by JEDEC in January 1996. (CX 887). Rambus responded to the dues invoice by a letter dated June 17, 1996, in which it informed JEDEC that it was not renewing its membership in the organization. (CX 887). 129 872. Also in December 1995, Rambus s patent counsel, Lester Vincent, sent Diepenbrock, Rambus s IF manager, materials relating to a proposed FTC consent order involving Dell Computer. (CX 1990 at 1; Diepenbrock, Tr. 6222). Vincent described the case as involving charges that Dell restricted competition in the personal computer industry and undermned the standard setting process by threatening to exercise undisclosed patent rights against computer companies adopting standard technology. (CX 1990 at 1). 873. " (L)egal guidance not to attend JEDEC escalated" after the "situation with Dell. (CX 2112 at 222 (Mooring, Dep.)). Rambus s lawyers felt that, although Rambus s situation was not the same as the situation in the Dell case, the risk that an equitable estoppel defense might be raised justified withdrawing tfom JEDEC, assuming that the benefits of attendance did not outweigh the risks. (CX 3124 at 196-97 (Vincent Infneon Dep. )). 874. Rambus s separation tfom JEDEC was formalized on June 17, 1996, when Rambus sent a letter to the JEDEC offce that stated: I am writing to inform you that Rambus Inc. is not renewing its membership in JEDEC. Recently at JEDEC meetings the subject of Ram bus patents has been raised. Rambus plans to continue to license its proprietary technology on terms that are consistent with the business plan of Rambus, and those terms may not be consistent with the terms set by standards bodies, including JEDEC. A number of major companies are already licensees of Ram bus technology. We trust that you will understand that Rambus reserves all rights regarding its intellectual property. Rambus does, however, encourage companies to contact Dave Mooring of Ram bus to discuss licensing terms and to sign up as licensees. To the extent that anyone is interested in the patents of Rambus, I have enclosed a list of Ram bus US. and foreign patents. Rambus has also applied for a number of additional patents in order to protect Rambus technology. (See CX 887). 875. Rambus included with the letter a list of patents but did not include any reference to patent applications. Nor did the list include the ' 327 patent. (CX 887). 876. The evidence is inconclusive regarding whether the ' 327 patent was left off of the list intentionally or inadvertently. (CX 887). 130 Ongoing Discussions of Rambus Patents by JEDEC Members After June 1996 877. In October 1996, t l (R 781 at 2 (in camera)). 878. In December 1996, Micron executive Jeff Mailoux wrote a memorandum to Micron CEO Steve Appleton that stated in part that: We have been investigating high speed DRAs and the intellectual property associated with them for some time now. . . . We have also been investigating the prior art related to the area of highspeed DRAs. From our research, we think many RAUS patents read on prior art or other patents. (RX 829 at 2). 879. The minutes of the March 1997 JC 42. 3 meeting reflect that during a presentation regarding an NEC proposal involving DDR SDRA, a representative stated that "(s)ome on the commttee felt that Rambus had a patent on that type of clock design." (JX 36 at 7). 880. Micron representative Terry Lee was present at the March 1997 JC 42. 3 meeting. Lee had raised the concern about a possible Rambus patent at the meeting that is reflected in the minutes. (Lee, Tr. 6957-58; JX 36 at 7). 881. The NEC representative s trip report for the March 1997 JEDEC meeting supports Lee s recollection, for it includes the following summary of the discussion regrading the NEC DDR proposal: Company Comments Micron This technque is patented by RAUS and they wil not agree to the JEDEC patent policy. Mosaid/VLSI This may be a future bus concept. Future bus was invented before RAUS became a company, so this may not be a valid patent. (RX 880 at 25). 131 882. The NEC DDR proposal, however, did not involve a "narrow bus" and was not packetized." (Lee, Tr. 6961). 883. Lee agreed that by March 1997, he thought that Rambus might have intellectual property claims relating not just to RDRAs but to the work of the JC 42. 3 commttee as well. (Lee, Tr. 6962-64). 884. On April 16, 1997, a Micron employee, Keith Weinstock, sent an email to various Micron employees that stated in part that "Rambus plans legal action to request royalties on all DDR memory efforts." (R 920 at 2). 885. At the time he prepared his April 16, 1997 email, Weinstock was a Micron account representative with responsibility for Intel. (Lee, Tr. 6700). 886. Weinstock sent his April 16, 1997 email, and its statement that "Rambus plans legal action to request royalties on all DDR memory efforts " to Jon Biggs, with a copy to Terry Walther, Jeff Mailloux, Terr Lee, Kevin Ryan, Gary Welch and Steve Trick. (RX 920 at 1). 887. At the time, Biggs was Weinstock' s predecessor as the Micron account representative for Intel. (Lee, Tr. 6967). Mailoux was Micron DRA Marketing Manager at the time. (CX 3133 at 44-45 (Mailoux, Micron Dep. )). Walther was a JEDEC representative for Micron. (Lee, Tr. 6594 6953). Welch was in Product Marketing at Micron, with responsibility for Rambus products. (Lee, Tr. 6967). Trick was a Micron employee responsible for module development. (Lee, Tr. 6973). Lee was in the Strategic Marketing department at Micron reporting to Mailoux. He also attended JEDEC meetings tfequently in the 1997-2000 time period. (Lee, Tr. 6591-95). Ryan was in a similar position as Lee and also attended JEDEC meetings in this time period. (Lee, Tr. 6601). 888. On April 17, 1997, Micron JEDEC representative Terr Walther responded Weinstock' s email and asked him to confrm the report about Rambus s intellectual property claims, asking "Does Rambus believe they have a patent on changing data on both edges of the clock? .. I think that is old technology. Can you find out what they think they have?" (R 920 at 1). 889. Weinstock responded to Walther s question: "Yes, Rambus feels DDR for any memory is under their patent coverage. James (Akyama, an Intel employee) said that Rambus has more IF than Intel has seen. He further stated the determning factor would be whether the courts take a ' broad or a narrow view of the patents.''' (RX 920 at 1). 890. The April 17, 1997 response by Weinstock was copied to Mailoux, Lee and all of the other recipients of Weinstock' s original email. (RX 920 at 1). 891. Lee testified that he understood Weinstock' s statement about Rambus s intellectual 132 property claims over "DDR for any memory" to be a reference to the DDR SDRA device that was then being discussed at JEDEC. (Lee, Tr. 6968). 892. Lee also understood that Weinstock was referrng to possible patent iningement lawsuits by Rambus when Weinstock wrote: "Rambus plans legal action to request royalties on all DDR memory efforts. " (Lee, Tr. 6971-72; see RX 920 at 2). 893. Lee testified that he did nothing at all to follow up on the reference to Rambus intellectual property claims regarding "DDR for any memory. " (Lee, Tr. 6702, 6972; see RX 920 at 1). 894. Lee testified that as far as he knows, none of the other recipients of Weinstock' April 17, 1997 email did anything to follow up on the reference to Rambus s intellectual property claims. (Lee, Tr. 6972-73). 895. Lee explained that he had not followed up with respect to the information regarding Rambus s possible intellectual property claims, and did not consider asking JEDEC to request RA" assurances tfom Rambus, because he "didn t believe this was true. " (Lee, Tr. 6981). 896. Afer reviewing the April 16 and 17, 1997 Micron emails during trial, 42. 3 chairman Gordon Kelley testified that he believed that the Micron JEDEC representatives who received the emails were obligated under the JEDEC patent policy to tell the JC 42. 3 commttee the information about Rambus s claims that is contained in the emails. (G. Kelley. Tr. 2748-49). 897. In May 1997, Rambus engineer Richard Crisp met with the Vice President of Engineering for VIA Technologies, a chip set manufacturer based in Taiwan. (R 924 at 1). 898. Crisp s email regarding the May 1997 meeting states in part that the VIA executive had: . . . Told me that he thinks that SyncLink is going to be stepping all over Rambus patents. I told him that no one can know for sure about any of that until chips exist, but that since we were first and have a lot of fundamental patents, it would not be a surprise to find that to be the case, and if it were, that I felt quite sure we would pursue protection of our IF rights. (R 924 at 1). 899. In July 1997, the offcial SyncLink Consortium minutes reflect a concern that the Consortium should "collect information relevant to prior art and Rambus filings" in anticipation that "Rambus wil sue individual companies" for patent iningement. (RX 966 at 3). 133 900. In July 1998, a Hynix executive sent an email containing "a list of Ram bus patents to a large group of DRA engineers and JEDEC representatives tfom such companies as Micron Texas Instruments, IBM, VLSI, Compaq, Mosaid and Siemens. (RX 1214 at 1). 901. The list of patents provided by the Hynix executive included the ' 327 patent that Rambus had left off the list of patents submitted with its JEDEC withdrawal letter. (R 1214 at 1). VI. RAMBUS WAS NOT IN VIOLATION OF ANY JEDEC RULES Rambus Was Not in Violation of the JEDEC Patent Policy 902. Rambus was not in violation of the JEDEC patent policy because that policy merely encouraged the voluntary disclosure of patents essential to practice JEDEC standards. (See 766- , supra). Not disclosing patents conformed not only to the policy but also was consistent with the conduct of other JEDEC members. (See F. 686-717 supra). There Is No Evidence that Crisp, During the Time Rambus Participated in JEDEC, Had Actual Knowledge that Rambus Had Claims that Could Be Asserted Against JEDEC-Compliant SDRAM or DDR SDRAM Products 903. Complaint Counsel have asserted that "when a JEDEC member company understands or believes that its patents bear upon specific aspects of JEDEC' s standardization work, that knowledge on the part of the company triggers a duty to disclose. " (Opening Statement, Tr. 17). 904. There is substantial evidence that it was a JEDEC representative s "actual knowledge " not his beliefs, that triggered whether disclosure obligations might exist. (Roden Tr. 624; 1. Kelly, Tr. 1970 2171-72; see also RX 669 at 3). 905. Rambus CEO, GeoffTate, testified that a statement in the June 1992 draft plan that we believe that Sync DRAs intinge on some claims in our filed patents" was based on a feeling" that "synchronous DRAs sure looked like they stem(med) tfom (our) inventions. (CX 543A at 17; CX 2073 at 221-22 (Tate, Micron Dep.)). Tate had "assumed" that broad patent applications had been filed to protect all ofRambus s inventions. (CX 2073 at 222 (Tate Micron Dep. ); CX 2088 at 57 (Tate, Infneon Trial Tr. )). 906. Crisp is not among the individuals listed as receiving the June 1992 draf plan. (CX 543A at 11). 907. Afer the 1992 Business Plan was prepared, a Rambus employee was assigned the task of determning what filed claims would be intinged by SDRAs. (CX 2073, Tate Micron Dep. at 222-23). The employee subsequently informed Tate that the filed claims were not as 134 broad as previously thought and did not cover the full range of what had been invented and described in the ' 898 application. (CX 2073 at 222-24 (Tate, Micron Dep. ); CX 2088 at 57- (Tate, Infneon Trial Tr.)). 908. Complaint Counsel also point to a June 1993 email by Rambus engineer Fred Ware that states that a claim in a Rambus patent application was "directed against SDRAs. (CX 1959 at 1). Complaint Counsel did not contend at trial, however, that in June 1993 Rambus had any claim in a pending application that covered any feature of SDRAs. The only Rambus patent claims that are alleged by Complaint Counsel to cover SDRAs are claims in the ' 961 and 490 applications; these claims were not filed until 1995. (See supra F. 960-62). 909. In their opening statement, Complaint Counsel asserted that Ware s June 1993 email referred to a May 1993 "amendment to Rambus s pending ' 651 application (application serial no. 07/847 651) related to the concept of programmable CAS latency and that this amendment was intended to cover programmable CAS latency when used in DRAs generally, including SDRAs that were the subject of JEDEC work." (Opening Statement, Tr. 84-85). However, all the claims in the May 1993 amendment to the ' 651 application contained the limitation that data address, and control information be "in the form of packets " a feature that is not found in SDRAs. (CX 1458 at 5-8). SDRAs, unlike RDRAs, do not receive information in the form of packets. (Rhoden, Tr. 402; Sussman, Tr. 1431-32; G. Kelley, Tr. 2573-74; Kellogg, Tr. 5298; Jacob, Tr. 5466-67). Complaint Counsel did not contend at trial that the claims contained in the May 1993 amendment to the ' 651 application covered programmable latency as used in JEDEC-compliant SDRAs. 910. Rambus s JEDEC representative, Richard Crisp, testified that during the time that Rambus was a JEDEC member, he: (1) had not seen any Rambus patent applications with claims over an SDRA that used any of the four features at issue here; and (2) did not know one way or the other whether Rambus s pending patent applications covered JEDEC-compliant SDRAs using any of those features. (Crisp, Tr. 3461- , 3540-43). 911. In March 1998, Joel Karp informed Rambus' s board of directors of the potential weakness ofRambus s existing patent claims. (Farmwald, Tr. 8231-34; CX 615 at 2). Karp also informed the board that he believed that he could improve the strength of the patent portfolio, but that it would take a year or two to do so. (Farmwald, Tr. 8231-32). 912. By July 1999 , " Mr. Karp reviewed the Company s strategic portfolio of current IP and plans for an additional strategic portfolio for extending the life of Ram bus IP. " (CX 622 2). He observed a number of weaknesses that could be addressed including a lot of new patent applications or amendments that could be filed, and was actively working on these projects. (Farmwald, Tr. 8237-38; CX 622 at 2). 913. It was not until mid- 1999 that a Rambus patent issued with claims that were ininged by JEDEC-compliant SDRAs or DDR SDRAs. (Farmwald, Tr. 8239-40; CX 623 at 4). 135 Rambus Did Not Misappropriate Information From JEDEC 914. Rambus began attending JEDEC meetings, in part, to learn what its competition was working on. (CX 837 at 1-2). 915. JEDEC 42. 3 Chairman Gordon Kelley testified that he and Siemens s JEDEC representative Wili Meyer were each reporting on JEDEC activities to a joint DRA development team that IBM and Siemens had created. (G. Kelley, Tr. 2620-21). 916. Kelley testified that he "did not understand that the use of JEDEC confdential information was an abuse as long as the people using the information were members." (G. Kelley, Tr. 2626). 917. Even today, JEDEC tries to enlist new members by pointing to the competitive advantages of membership, or perhaps the disadvantages of non-membership. (CX 302 at 17 (Rhoden presentation states that "(i)fyou are not there, your competition may be deciding your future. )). 918. Rambus used the information it obtained at JEDEC to help refine the claims in its pending patent applications to ensure that its claims would cover the JEDEC standards. (CX 2092 at 192 (Crisp, Infneon Trial Tr.). There Were No Prohibitions Which Precluded Rambus From Seeking Patent Protection For Inventions that Related to JEDEC Standards 919. The EIA Legal Guides, which governed JEDEC standardization activities while Rambus was a JEDEC member, state explicitly that " (s)tandards are proposed or adopted by EIA without regard to whether their proposal or adoption may in any way involve patents on articles materials, or processes. " (CX 204 at 4). 920. The EIA' s January 22, 1996 comment letter to the FTC in connection with the Dell litigation states in part that "(a)llowing patented technology in standards is procompetitive. (R 669 at 2). The letter explains that " (b)y allowing standards based on patents, American consumers are assured of standards that reflect the latest innovation and high technology the great techncal minds can deliver." (RX 669 at 2-3). 921. The EIA' s January 22, 1996 comment letter to the FTC also states that " (s)tandards in these high-tech industries must be based on the leading edge technologies. Consumers will not buy second-best products that are based only on publicly available information. They demand and deserve the best technology these industries can offer. " (RX 669 at 4). 136 922. The EIA's January 22, 1996 comment letter to the FTC also states that " (e)ven if knowledge of a patent comes later in time due to the pending status of the patent while the standard was being created, the important issue is the licensing availability to all parties on reasonable, non-discriminatory terms." (RX 669 at 4). 923. EIA General Counsel John Kelly testified that even though EIA would prefer not to include patented technologies in EIA standards, there is no objection to having standards that incorporate patented technologies, as long as the patents are available to all potential licensees on reasonable and nondiscriminatory terms. (1. Kelly, Tr. 2072). 924. Throughout the time period that Rambus was a member, JC 42. 3 routinely passed ballots to adopt technology as part of its standards despite its awareness of patent-related issues. At the March 1993 JC 42.3 meeting, for example, the commttee voted to pass a ballot on Mode Register Timing for the SDRA draft specification even though Hitachi raised a "patent alert. (JX 15 at 5). 925. At the March 1993 JC 42. 3 meeting, the commttee also considered ballots for Self- Retfesh Entry/Exit, DQM Latency Reads/Writes, and Auto-Retfesh for the SDRA draft specification. (JX 15 at 8-9). The minutes state that both Hitachi and Mosaid raised a "patent alert" or a "patent concern" with respect to each ofthese features. (JX 15 at 8, 9). The commttee voted unanimously to pass these ballots. (JX 15 at 8, 9). 926. At the March 1993 JC 42. 3 meeting, the commttee also considered a ballot for a Write Latency = 0 for the SDRA draft specification. With regard to this ballot, the minutes state that Mosaid raised a patent issue. (JX 15 at 5-6). The minutes also state , " The Commttee is aware of the Hitachi patent. It was noted that Motorola has already noted they have a patent. IBM noted that their view has been to ignore patent disclosure rule because their attorneys have advised them that if they do then a listing maybe construed as complete. " (JX 15 at 6). The commttee voted unanimously to pass this ballot. (JX 15 at 6). At that meeting, the commttee also voted unanimously to send all SDRA ballots to the JEDEC Council for standardization. (JX 15 at 14). 927. At the very next JC 42. 3 meeting, which was held before the SDRA ballots had been voted on by the JEDEC Council, the 42. 3 Commttee reviewed an analysis of patents relating to SDRAs. The analysis, which was prepared by Chipworks, included a discussion of several Hitachi patents related to SDRAs that were described as "powerfl" (CX 53A at 13), as well as SDRA-related patents held by Motorola and other JEDEC members. (CX 53 A at 14). 928. No witness who was present at the March and May 1993 JC-42. 3 meetings testified that any criticism was leveled against JEDEC members who had obtained patents relating to SDRAs. 137 Rambus Followed the Advice of Its Legal Counsel in Determining Its Legal Obligations to JEDEC 929. Complaint Counsel asserts that Rambus "acted with knowledge that itwas violating JEDEC' s rules relating to intellectual property disclosures. (Complaint Counsel' s Pre-Trial Brief, at 196). 930. Shortly after it joined JEDEC, Rambus sought the legal advice of its outside patent counsel, Lester Vincent, in connection with its participation in JEDEC including the preparation and revision of its patent applications. (CX 3125 at 279-80 (Vincent, Dep. )). 931. In March 1992, Richard Crisp and his supervisor, Allen Roberts, talked to Vincent about JEDEC-related issues. (CX 3125 at 310-315 (Vincent, Dep. )). Afer discussing JEDEC with Vincent , " the two key things that (Crisp) walked away tfom the meeting understanding was that Rambus should not go and promote a standard, and we should not mislead JEDEC into thinking that we wouldn t enforce our property rights. " (Crisp, Tr. 3470-71). 932. Vincent's time sheets show that at around the time he gave Crisp this advice, he reviewed one or more "JEDEC publications. " (CX 1937 at 12). 933. Crisp followed Vincent' s advice and did not promote a technology for standardization at any time during Rambus s membership. (Crisp, Tr. 3470). 934. An email that Crisp wrote in December 1995, almost four years later, shows that he was stil mindful of Vincent's advice at that time. He wrote that he understood that Rambus should not "intentionally propose something as a standard and quietly have a patent in our back pocket. . . . " (CX 711 at 188). As he also stated at the time, he was "unaware of us doing any of this or of any plans to do this." (CX 711 at 188). Crisp testified that this December 1995 passage referred to "what we would have to do and what we should not do in the event that we were to propose the R-module as a standard." (Crisp, Tr. 3485). 935. When Crisp was asked at JEDEC meetings on two occasions to comment about Rambus s intellectual property, he declined to comment each time, and the JEDEC members who testified at trial understood that he had declined to comment. (F. 807- , 842- supra). Crisp also testified that no one had informed him that his refusal to comment violated any JEDEC rule or policy. (Crisp, Tr. 3490-91). 936. Crisp was also advised by Vincent, in the 1992 time tfame, about the importance of keeping patent applications confdential. Crisp testified that Vincent "told us to not disclose our patent applications. They were confdential." Crisp followed this advice. (Crisp, Tr. 3496). 138 937. In letters transmitting copies ofRambus s patent applications, Vincent reminded Rambus employees to "keep in mind that this information is confdential." (CX 1951 at 2; CX 1945 at 2). 938. Crisp was present at a JEDEC meeting when an IBM representative stated that he would not disclose intellectual property at JEDEC meetings. Crisp indicated that he understood tfom that statement that such disclosures were not required. (Crisp, Tr. 3505-07). During the Time of Its Participation in JEDEC Rambus Had No Intellectual Propert Interests That It Would Have Been Required To Disclose Even If Disclosure Was Mandatory Rambus Had No Patents That It Was Required To Disclose 939. The parties stipulated that as of January 1996, Rambus held no issued US. patents that were essential to the manufacture or use of any device manufactured in compliance with any JEDEC standard. (First Set of Stipulations, Stip. 10). 940. The only patent that Complaint Counsel allege Rambus should have disclosed to JEDEC is US. Patent No. 5 513 327 (the ' 327 patent). Complaint Counsel allege that disclosure of the ' 327 patent was required because claims 1 and 7 of the patent could have been reasonably construed by an engineer to cover a JEDEC-compliant SDRA that also incorporated certain dual-edged clocking proposals and because those claims would read on the JEDEC DDR SDRA standard. (Jacob, Tr. 5541- , 5551-60). 941. The proposals or presentations that Complaint Counsel raise in this regard are: (1) a presentation by Willam Hardell of IBM referenced in the May 1992 minutes of the JEDEC 42. subcommttee (the "Hardell presentation ) (CX 34 at 32; Jacob, Tr. 5542), (2) a "Future SDRA Features Survey Ballot" referenced in the December 1995 minutes of the JEDEC 42. subcommttee (the "Survey Ballot")(JX 28 at 34-35; Jacob, Tr. 5543-44), and (3) a presentation by Samsung entitled "Future SDRA " referenced in the March 1996 minutes of the JEDEC 42. subcommttee (the " Samsung presentation ) (JX 31 at 71; Jacob, Tr. 5544). 942. The ' 327 patent issued on April 30, 1996 and was publicly available as of that date. (CX 1494 at 1). All of the proposals or presentations referenced by Complaint Counsel as supposedly triggering a disclosure obligation with respect to the ' 327 patent were made before the ' 327 patent issued. 139 943. Complaint Counsel's patent law expert, Mark Nusbaum, did not testify as to whether claims of the ' 327 patent related to JEDEC work. 944. Professor Jacob, who testified on behalf of Complaint Counsel regarding the alleged relationship between the ' 327 patent and JEDEC work, has no patents to his name and has never previously done any claims analysis ofthe type he presented in this matter with respect to the ' 327 patent. (Jacob, Tr. 5624, 5650). The ' 327 Patent Contains Various Limitations 945. Professor Jacob concedes that Claim 1 of the ' 327 patent "describes a specific implementation" of dual edge clocking, including the "implementation detail" that the DRA contains two input receivers with one receiver latching information in response to the rising edge of a clock signal and the other receiver latching information in response to the fallng edge of the clock signal. (CX 1494 at 23; Jacob, Tr. 5546-47). 946. Professor Jacob also concedes that claim 7 of the ' 327 patent describes a specific implementation of dual edged clocking where the DRA "toggle( s) between two output drivers through a multiplexer. " (CX 1494 at 23; Jacob, Tr. 5548). Rambus Had No Duty To Disclose the ' 327 Patent Based On the Hardell Presentation 947. The Hardell presentation related to IBM' s "toggle mode" DRA. (G. Kelley, Tr. 2514). IBM' s toggle mode was an asynchronous design. (Jacob, Tr. 5608; Soderman Tr. 9398). 948. The Hardell presentation noted that it has " Synchronous RAS/CAS." (CX 34 32). This makes it an asynchronous DRA, according to Professor Jacob' s definition of asynchronous DRAs as "those who are driven off the RAS and CAS signals where the RAS and CAS actually control the operation ofthe DRA rather than a clock." (Jacob, Tr. 5394). 949. JEDEC-compliant SDRAs are synchronous DRAs with synchronous RAS and CAS signals; the Hardell presentation described an asynchronous DRA with an asynchronous RAS/CAS interface. (CX 34 at 30-32). 950. The Hardell presentation gave no details about implementation of the dual-edged clocking feature, stating simply: "dual clock edge." (CX 34 at 32). 951. The Hardell presentation was referenced in a memorandum discussing presentations at a meeting of a task group in Dallas in April 1992, and no evidence was presented at trial that the Hardell presentation was ever balloted at JEDEC. (CX 34 at 4 32). 140 Rambus Had No Duty To Disclose the ' 327 Patent Based On the Survey Ballot 952. The Survey Ballot was circulated on or about October 30, 1995 to JEDEC members to determne what features JEDEC members might want to include in future DRAs. (JX 28 at 34-48; CX 260; Lee, Tr. 6636). 953. With respect to dual-edge clocking, the result ofthe Survey Ballot was that there was "mixed support" for "using both edges ofthe clock for sampling inputs. " (JX 28 at 35). 954. Complaint Counsel did not present evidence suffcient to find that the Survey Ballot was ever balloted and therefore it would not have triggered the patent policy. Rambus Had No Duty To Disclose the ' 327 Patent Based On the Samsung Presentation 955. With respect to dual-edge clocking, the March 1996 Samsung presentation stated only that "Data in sampled at both edge (sic) of Clock into memory. " The presentation went on to state: "Use both edge (sic) of the Strobe clock to sample the memory Data into Controller. (JX 31 at 71). 956. Complaint Counsel did not present evidence suffcient to find that the Samsung presentation was ever balloted and therefore it would not have triggered the patent policy. Complaint Counsel Did Not Provide Suffcient Evidence to Determine Whether the Presentations Would Trigger the Patent Policy 957. Complaint Counsel has not shown that there were suffcient implementation details presented in the Hardell presentation, Survey ballot, or Samsung presentation from which to determine whether the presentations could be construed as covering claims in the ' 327 patent. (See CX 34; JX 28, JX 31). 958. Rambus has not asserted the ' 327 patent against any SDRA or DDR SDRA devices. (See First Set of Stipulations, Stip. 14). Rambus Had No Undisclosed Patent Applications That It Was Required to Disclose, Even if the Policy Required Disclosure 959. The parties have stipulated that prior to the adoption of the JEDEC SDRA standard in 1993 , Rambus had no undisclosed claims in any pending patent application that, if issued, would have necessarily been intinged by the manufacture or use of any device 141 manufactured in accordance with the 1993 JEDEC SDRA standard. (First Set of Stipulations Stip. 9). 960. Despite this stipulation, Complaint Counsel argued that the following claims of Rambus patent applications should have been disclosed to JEDEC: (1) (2) (3) (4) Claims 151 , 159, 160, 164, 165 and 168 of application serial no. 07/847 961 (the ' 961 application), because they allegedly cover JEDECcompliant SDRAs (Nusbaum, Tr. 1544-45; Jacob, Tr. 5507, 5523-28); Claims 183 , 184, and 185 of application serial no. 08/469 490 (the ' 490 application), because they allegedly cover JEDEC-compliant SDRAs (Nusbaum, Tr. 1572-73; Jacob, Tr. 5528-32); Claims 151 , 152, 166 and 167 of application serial no. 07/847 692 (the 692 application), because they allegedly cover a presentation made by NEC that is contained in the September 1994 minutes of the JEDEC 42. subcommttee (JX 21 at 91; Nusbaum, Tr. 1584; Jacob, Tr. 5535 , 5540); and Claim 151 and 152 of application serial no. 08/222 646 (the ' 646 application), because it allegedly covers the Hardell presentation, the Survey Ballot, and the Samsung presentation (Nusbaum, Tr. 1597-98; Jacob, Tr. 5550). 961. The claims ofthe ' 961 application that Complaint Counsel allege covered JEDECcompliant SDRAs, claims 151 , 159, 160, 164, 165 , and 168, were added in an amendment filed on January 6, 1995. (CX 1504 at 216-26; Nusbaum, Tr. 1544-45; Fliesler, Tr. 8847). In an offce action dated April 16, 1995 , the patent examiner rejected all ofthe claims pending in the 961 application. (CX 1504 at 227-39). Among other grounds, claims 151- 165 were rejected as indefinite. (CX 1504 at 229). All of the claims in the ' 961 application that allegedly covered JEDEC-compliant SDRAs were cancelled by Rambus on June 23 , 1995. (CX 1504 at 258; Fliesler, Tr. 8847-48). 962. The claims of the ' 490 application that Complaint Counsel allege covered JEDECcompliant SDRAs, claims 183 , 184 and 185, were added in a preliminary amendment filed on June 23 , 1995. (CX 1504 at 258 264-66; Nusbaum, Tr. 1572-73; Fliesler, Tr. 8852). Afer a restriction requirement tfom the patent offce, Rambus elected to pursue other claims. Claims 183 , 184 and 185 were withdrawn tfom further consideration as of November 27, 1995. (CX 1504 at 274-75; Fliesler, Tr. 8852-54). 963. Claims 151 and 152 of the ' 692 application were filed in a preliminary amendment mailed on June 28, 1993. (CX 1502 at 205 208; Fliesler, Tr. 8864-65). In an amendment mailed 142 on October 23 , 1995, claims 151 and 152 wem amended and claims 166 and 167 were added. (CX 1502 at 233-35; Fliesler, Tr. 8864-65). 964. Complaint Counsel has not shown that, upon a formal iningement analysis, claims 151 and 152 of the ' 692 application (whether before or after the October 23 , 1995 amendment) and claims 166 and 167 might cover devices built according to the September 1994 NEC presentation. (JX 21 at 91; Fliesler, Tr. at 8866-67). 965. Claim 151 of the ' 646 application was mailed on September 6, 1994. (CX 1493 at 183-85; Fliesler, Tr. 8856). In an offce action dated January 24, 1995 , the patent examiner rejected claim 151 for, among other reasons, being indefinite. (CX 1493 at 212 215). Claim 151 was canceled in an amendment filed on September 14, 1995. (CX 1493 at 243; Fliesler, Tr. 8856- 57). The ' 327 patent, which issued tfom the ' 646 application, did not contain claim 151. (CX 1494; Nusbaum, Tr. 1617). 966. Claim 151 was filed over two years after the Hardell presentation, and before the Samsung presentation or the issuance of the Survey Ballot. (CX 1493 at 183-85; Fleisler Tr. 8856; CX 34 at 32; JX 28 at 34-35; JX 31 at 71). Thus, claim 151 was not pending at the time of any of the presentations that allegedly triggered its disclosure. 967. Claim 152 of the ' 646 application issued as claim 1 ofthe ' 327 patent. (CX 1493 at 223-24; CX 1494 at 23). Rambus Withdrew From JEDEC Before Formal Work On the Standardization of the DDR SDRAM Began 968. Rambus attended its last JEDEC meeting in December of 1995. On June 17, 1996 Rambus notified JEDEC that it would not pay its dues for 1996 and that it would no longer be a JEDEC member. (CX 2104 at 853-54 (Crisp, Micron Dep.); CX 887 at 1). 969. The DDR SDRA standard received JC 42. 3 commttee approval in March 1998 but was not published until 2000. (CX 375 at 1-3; JX 57). 970. The DDR SDRA standard received JEDEC Board of Director approval in 1999. (Rhoden, Tr. 743). 971. The first time that a balloted item was approved as part of the JEDEC DDR SDRA standard was June 1997. (CX 375 at 2). 972. An email authored by JEDEC Board Chairman Desi Rhoden in March 1998 shows that the first presentation leading to the DDR SDRA standard occurred in December 1996 afer Rambus had withdrawn tfom JEDEC. (CX 375 at 1-2). 143 973. On March 9, 1998, Rhoden sent an email to Ken McGhee, the JEDEC Secretary, for forwarding to all JC 42 members. (Roden, Tr. 1192-93; CX 375). The email was an effort by Rhoden to recap what had transpired in the DDR SDRA standardization process. (Roden Tr. 1195). 974. Rhoden s March 9, 1998 email states in part: (W)e could have finished the DDR standard sooner if only we had started earlier. Let us recap what has transpired with DDR: 1. A lot of private and independent work outside of JEDEC for most of 1996 (here is where we missed a good opportunity to start early). 2. December 96 - A single overview presentation of a DDR proposal at a JC 42 meeting. 3. March 97 - Many (5 as I remember) presentations of very different proposals at JEDEC (no where near the consensus that was supposedly built outside of the commttee). None of these were compatible with each other. At this meeting the decision was made to finally get serious and set up a special meeting for April 97. 4. April 97 - Real, focused, dedicated work begins at a special meeting. Many very good ideas and a lot of truly animated discussion. June 97 - First ballots on DDR pass commttee. 6. July 1997 - A second special meeting where the last of the basic concepts were articulated and sent out for ballot. 7. Sept 97 - The diamond in the rough took its basic shape (there were 2 very similar, but stil different forms). (CX 375 at 1-2). 975. Rhoden s March 1998 email thus dates the first presentation to JEDEC of a DDR SDRA proposal to December 1996. (CX 375 at 1). 976. Rhoden s email states that the DDR device was being developed "outside of JEDEC" in 1996. (CX 375 at 1). 144 977. In an April 1997 presentation, Rhoden stated: "DDR & SLDRA were Introduced In JEDEC in Dec 96." (R 911 at 3). 978. The initial DDR SDRA presentation that Rhoden referred to in his March 1998 email and his April 1997 presentation was made by Fujitsu in December 1996. (Rhoden Tr. 1198; RX 911 at 3; CX 375 at 1). This presentation, identified in the minutes of the JC 42. subcommttee as "Fujitsu Double Data Rate SDRA " was designated as a "first showing. (JX 35 at 6, 34-42). 979. Desi Rhoden was in a position to know about the dates described in his March 1998 emaiI. HehasplayedaleadershiproleatJEDECforquitesometime. (Roden Tr. 1191). He is currently chairman of the JC 42 commttee, which contains the JC 42.3 subcommttee. (Roden Tr. 1191). He has also been chairman of the 42. 3 subcommttee and is currently chairman ofthe JEDEC Board of Directors. (Roden, Tr. 1190). In 1998, Rhoden was very actively involved in the DDR SDRA standardization process within the JEDEC 42 commttee. (Rhoden, Tr. 1191- 92). 980. There is other contemporaneous evidence that work on the DDR SDRA device did not begin, even outside of JEDEC, until the summer of 1996. An IBM presentation on DDR SDRA dated March 17, 1997 notes that "Industry has been working on DDR definition for 6-9 months " that is, beginnng at some point between approximately mid-June and mid-September 1996. (RX 892 at 1). Initially, this work consisted of "small supplier consortiums and individual supplier/user meetings." (R 892 at 1). Like Rhoden s testimony, the IBM document dates the first "Offcial DDR presentations" at JEDEC to December 1996, referrng (again) to the first showing by Fujitsu. (R 892 at 1). 981. A March 10, 1997 Mitsubishi memorandum regarding "DDR SDRA Specification Plannng History and Recent Trends" confrms that DDR efforts began outside of JEDEC in the summer of 1996, with "eight companies. . . meeting once every 2 weeks to quickly plan DDR specifications." (R 885A at 1). The Mitsubishi memorandum s first mention of JEDEC work relating to DDR SDRA is the first showing by Fujitsu in December 1996. (R 885A at 1). 982. As Gordon Kelley, Chairman of the JC 42. 3 subcommttee, explained, after a company left JEDEC, it had no duty to disclose anything to JEDEC. (G. Kelley, Tr. 2700). Document Destruction by Rambus 983. In March 1998, there was "growing worry" within Rambus about ..email back-ups as being discoverable information" in future litigation. (CX 1005 at 1). 984. Rambus executives decided to destroy emails archived on the company s backup system after three months. (CX 1744A at 94 ("3 months might be ok"); CX 1744A at 104 (May 145 1998 management staff meeting: "Backups kept for three months ); CX 2114 at 137 (Karp, Dep. )). 985. Rambus did not preserve emails tfom the early 1990' s that were stored on Macintosh backup tapes. (CX 2114 at 141 (Karp, Dep. ) (" those were the first tapes that were destroyed" )). 986. Employees could stil maintain their own email archives for whatever time period they desired. Employees were told to maintain their own archives if they wanted to maintain email files for longer than three months. (CX 2102 at 80-81 (Karp Dep.); CX 1031). 987. Rambus CEO Geoffey Tate and Karp had a one-on-one meeting at which they discussed reviewing pre-June 1996 backup tapes. (CX 1744A at 136 ("Review backup tapes for pre-June 1996, Check for files ); CX 2114 at 145-6 (Karp, Dep. )). 988. On May 14, 1998, Karp sent an email to all Rambus engineers and senior managers regarding "Backup Strategy/Document Retention Policy." (CX 1031 at 1). He informed them that " (e)very Rambus employee wil be involved" in Rambus s document retention policy. (CX 1031 at 1). Karp announced that he expected to have "a company meeting in early June to kick off the program." (CX 1031 at 1). He invited questions in face-to-face discussions, but preferred that senders of any emails "keep the distribution narrow. " (CX 103 1 at 1). 989. In June 1998, Karp outlined a plan to implement Rambus s document retention policy. (CX 1744A at 126 ("Exec approval of doc. ret. policy, Presentation of details to exec Presentation to managers and key individuals with outside counsel, Presentation to staff via division meetings, Implementation mid-August"); CX 2114 at 1442-43 (Karp, Dep. )). 990. In July 1998, Karp disseminated Rambus s two-page written document retention policy to all Rambus employees. (CX 1040 at 1-2; Diepenbrock, Tr. 6230; CX 2114 at 156- (Karp, Dep. )). 991. Afer distributing the written policy, Karp and an attorney tfom Cooley Godward held a meeting with all Rambus employees to "kick off' the document retention policy. (Diepenbrock, Tr. 6230; Crisp, Tr. 3419; CX 2102 at 98-99 (Karp, Dep.); CX 2114 at 157 (Karp, Dep. 992. Whle explaining the document retention policy to Rambus employees, Karp told staff to destroy emails because they could be discoverable in litigation. (CX 1264 at 1 ("EMA - THROW IT AWAY . Email Is Discoverable In Litigation Or Pursuant To A Subpoena. Elimination of email is an integral part of document control. In General, Email Messages Should Be Deleted As Soon As They Are Read"); CX 2114 at 161 (Karp, Dep. ) (" We know all e-mail is discoverable; there s no question about that. So the real question becomes what are you required to save and what should you not save. )). 146 993. The document retention instructions were also summarized in slides that Karp used when he delivered presentations to staff The slides Karp presented to all Rambus employees instructed Rambus employees to , " LOOK FOR THIGS TO KEEP." (CX 1264 at 1). 994. Rambus s former in-house counsel Anthony Diepenbrock was told that Rambus did not want to keep documents around because they were " (d)iscoverable in a lawsuit. (Diepenbrock, Tr. 6234-35 ("Q. And when you say you were told Rambus didn t want to keep these documents around because they were discoverable, when you say ' discoverable ' you are talking about in a subsequent litigation like we are in right here, right? . . . A. Discoverable in a lawsuit, right )). 995. As a result of directives tfom Karp, Diepenbrock, Rambus s in-house counsel purged his documents and files in the summer on 1998. (Diepenbrock, Tr. 6235-36). 996. In the weeks following the initial meeting, Karp held several training sessions regarding the document retention plan. (CX 2102 at 98 (Karp, Dep. )). 997. Karp explained Rambus s document retention policy to all Rambus employees. (CX 2102 at 104 (Karp, Dep. )). 998. In September 1998, Rambus celebrated a corporate-wide "Shredder Day." (CX 1044 at 1; CX 1051 at 1 ("Thursday is Shred Day 1998. . . . Please leave your burlap bags in the hallway. . . We wil have a Shred Day Celebration in the new 1 st floor open area. . . If you have any questions regarding our Document Retention Policy, please see Joel (Karp)"); Crisp, Tr. 3422; CX 2102 at 106 (Karp, Dep. ) (" we had one day where we had kind of a spring cleaning. . . one of the many Valley shredding companies (came) in with their kind of industrial shredders )). 999. In one day alone, in the span of five hours, Rambus destroyed as much as 20 000 pounds of business records. (CX 2102 at 108 (Karp, Dep.) (Rambus delivered "a lot of stuff' to the shredding company; the "stuff (was) being basically piled pretty high on carts. "); CX 1052 at 1). 1000. Karp testified that he "did a little bit of spot checking" with Rambus employees and sat and watched over their shoulder" to insure compliance with the document retention policy. (CX 2102 at 97-98 (Karp, Micron Dep. )). 1001. In September 1998, Karp had a one-on-one meeting with Rambus CEO Geoffey Tate during which Karp inquired whether Tate and other board members had cleaned out their files. (CX 1744A at 141 ("Doc. Retent, Geofffiles?, Board members?"); CX 2114 at 148 (Karp, Dep. )). 147 1002. Rambus instructed Lester Vincent, an attorney with its outside patent law firm Blakely, Sokoloff Taylor & Zafman, to destroy Rambus-related files. (CX 3129 at 530 (Vincent Dep. ) (" (Karp) discussed the Rambus document retention policy that he wanted me to implement. ); CX 3126 at 410 (Vincent, Dep.); CX 2114 at 183-84 (Karp, Dep. )). 1003. At Rambus s request, Vincent destroyed a variety of documents tfom the left hand side of his files, including various "prosecution documents" such as "patent prosecution files for issued patents. . . claiming priority to the 1990 Farmwald, Horowitz application." (CX 3126 408 (Vincent, Dep.); CX 3129 at 530- , 536, 539-40 (Vincent, Dep. )). 1004. Vincent also destroyed various "drafs, handwritten notes, letters or faxes, and maybe drawings " including correspondence tfom Rambus to Blakely, Sokoloff and vice versa Vincent' s own handwritten notes and those of other lawyers tfom his firm, drafs of patent applications and amendments, draft handwritten drawings or informal drawings, electronic versions of such documents, and audio tapes of meetings with inventors. (CX 3129 at 531- (Vincent, Dep. ); CX 3126 at 425-26 (Vincent, Dep. )). 1005. Some of the copies Vincent destroyed were the "only documents in existence. (CX 3129 at 539-40 (Vincent, Dep. )). 1006. Vincent carried out the document destruction at various points in time, beginnng several months after the initial instructions he received tfom Rambus in 1997 and early 1998. (CX 3126 at 418 422 (Vincent, Dep. )). 1007. Vincent briefly suspended the document destruction after Rambus filed a lawsuit against Hitachi in 2000. (CX 3129 at 534-35 (Vincent, Dep. )). 1008. Afer the hiatus in document destruction during the pendency of the Hitachi litigation, Vincent's law firm recommenced destroying documents. (CX 3129 at 535 (Vincent Dep. )). Document destruction continued at least until Rambus filed the Infneon suit in August 2000. (CX 3126 at 424 (Vincent, Dep.)); CX 1329 at 542 (Vincent, Dep. )). 1009. CX 711 is a 199 page collection of emails authored by Richard Crisp that were preserved on Rambus s main server when Crisp transferred the messages tfom one laptop computer to another via the server. (Crisp. Tr. 3587-91). These documents were preserved were produced in discovery, and were admitted into evidence. (Crisp, Tr. 3572- , 3588-92). 148 IX. . RAMBUS HAS MONOPOLY POWER IN THE RELEVANT MARKTS Relevant Markets Product Markets 1010. Technology markets are markets for ideas or inventions where technology itself is a product. (McMee, Tr. 7324). The demand for DRA technology is derived tfom the demand for DRAs, and the demand for DRAs is derived tfom the final products in which DRA used. Ultimately the demand for the technology traces back to the demand for the final good. (McMee, Tr. 7182, 7198-99). 1011. Often in technology markets tfequent trades have historically not taken place. Therefore there is little historical price and quantity data. (McMee, Tr. 7321). In lieu of data pertaining to actual trades, serious consideration of a technology by JEDEC participants suggests that informed buyers of the technology view those technologies as significant substitutes and hence price-constraining substitutes. (McMee, Tr. 7333-34). 1012. The relevant purchasers or buyers in this case include DRA manufacturers. (McMee, Tr. 7323-24; Rapp, Tr. 9969-72). 1013. There are four relevant technology markets in this case: (1) the latency technology market (McMee, Tr. 7364); (2) the burst length technology market (McMee, Tr. 7373); (3) the data acceleration technology market (McMee, Tr. 7380); and (4) the clock synchronization technology market (McMee, Tr. 7385-86). 1014. In addition, it can be analytically useful to consider a "cluster" market. (McMee Tr. 7390-92). A "cluster" market would consider each ofthe four relevant product markets as a collection, based on the logic that the products are used in the same products, though strictly speaking they are not substitutes for one another. (McMee, Tr. 7390-92). The "cluster" market utilized in this case is the synchronous DRA technology market. (McMee, Tr. 7390-91). 1015. Respondent does not challenge Complaint Counsel' s product market definitions. Respondent' s economic expert, Dr. Rapp, testified that "relevant market is not crucial to understanding competition and market power in this setting. " (Rapp, Tr. 10036). Geographic Market 1016. The relevant geographic market for each relevant product market is the world. (McMee, Tr. 7393). 149 1017. The relevant geographic market for each relevant product market is the world because: buyers of technology typically do not care about the geographic source of technology; technologies tend to be licensed worldwide; technologies tend to flow across national borders; downstream products are produced and used worldwide; and transportation costs of both technology and DRAs are negligible. (McMee, Tr. 7393-95). Monopoly Power 1018. Rambus possesses monopoly power in the relevant technology markets. (F. 1019- 29; McMee, Tr. 7420-21). 1019. Rambus s economic expert, Dr. Rapp, does not contest that Rambus possesses market power in the four technology markets. (Rapp, Tr. 10046). Dr. Rapp testified that his opinion is that the market power that Rambus possesses in these four technologies arises solely out of the distance between the cost-performance qualities of the Rambus technologies and the next best alternative. " (Rapp, Tr. 10260). Market Share 1020. The percentage of total DRA production in the world today that is subject to Rambus s patent claims is in the upper nineties. (McMee, Tr. 7430). 1021. Rambus claims that approximately ninety percent of the entire DRA market is covered by Rambus patents. (CX 1386 at 4 ("Today - We are on the cusp of achieving our original (goal) - SDRA+DDR +RDRA:;:;90% of the DRA market - SDRADR: -20% paying us royalties now; all by 0I/E")); CX2067 at 171 (Davidow, Dep. ) (" Q. SO am I right, then that it's Rambus s position () that any SDRA or RDRA being used in main memory PCs today (January 31 2001) are covered by their patents? . . . (A) I would say that it is highly likely that is true. )). Assertion of Patents 1022. Rambus believed that certain of its patents cover SDRA and DDR SDRA products. (CX 1353 at 7 ("Intellectual Property. .. Strategic Patent Portfolio 1: SDRADR/Controllers all intinge ); CX 1382 at 33 ("Non-Compatible License Terms, All agreements cover SDRA, DDR and logic ICs which control these memories ); CX 1364 at 1- (in camera)). 1023. Rambus has asserted that its innovations include "Programmable latency register on a SDRA " " Programmable burst technques implemented on a SDRA " " DLL implemented on a SDRA " and "Double data rate. " (CX 1371 at 5; CX 1383 at 4; see also CX 1363 at 1). 150 1024. Rambus has asserted that "programmable latency on a DRA and Programmable burst on a DRA " as used in SDRAs, and "DLL implemented on a DRA and "Double data rate " as used in DDR SDRAs, are Rambus innovations covered by its patents. (CX 1363 at 3). 1025. Rambus has asserted that its issued patents cover programmable CAS latency, as described and depicted in JEDEC SDRA and DDR SDRA data sheets and individual company data sheets. (CX 1371 at 46, 53 (asserting that the phrase "value which is representative of a time delay after which the memory device responds to a read request" in claim 44 ofRambus s ' 365 patent corresponds to the CAS latency portion of the mode register diagram in the JEDEC 64M DDR SDRA Data Sheet); CX 1383 at 47, 51 (same); CX 1338 at 20 (asserting that same language tfom claim 23 ofRambus s ' 195 patent corresponds to the CAS latency portion ofthe mode register in Micron s 16M SDRA Datasheet); CX 1338 at 41 (similar language tfom Rambus s ' 918 patent compared to the CAS latency portion of Micron 16M SDRA Datasheet)). 1026. Rambus has asserted that its issued patents cover programmable burst length, as described and depicted in JEDEC SDRA and DDR SDRA data sheets and individual company data sheets. (CX 1371 at 64, 68 (asserting that the phrase "a first amount of data to be output onto a bus in response to a read request" in claim 1 of its ' 214 patent corresponds to the burst length portion of the mode register diagram in the JEDEC 64M DDR SDRA Data Sheet); CX 1383 at 60 64 (same); CX 1371 at 31 36 (asserting that similar language tfom Rambus 918 patent corresponds to the burst length portion of the mode register in Micron s 16M SDRA Datasheet)). 1027. Rambus has asserted that its issued patents cover on-chip DLL as depicted in JEDEC SDRA and DDR SDRA data sheets. (CX 1371 at 84-85 (asserting that the term delay locked loop" in claim 11 of its ' 214 patent corresponded to the indication "DLL" in the functional block diagram of the JEDEC 64M DDR SDRA Data Sheet)). 1028. Rambus has asserted that its patents cover use of programmable CAS latency, programmable burst length, on-chip DLL and dual edge clock in JEDEC-compliant SDRAs and DDR SDRAs. (Lee, Tr. 6776-77; Rhoden, Tr. 529-31). 1029. Rambus has also asserted that certain of its issued foreign patents cover use of programmable CAS latency, programmable burst length, on-chip DLL and dual edge clock in certain SDRAs and DDR SDRAs. (Bechtelsheim, Tr. 5884-85; CX 1268 at 1- , 13- 14). 151 JEDEC Standardization Rambus s Market Power Is Not Attributable to the Inclusion of Its Technology In JEDEC Standards 1030. Regarding standardization and market power, Rambus offered the testimony of Dr. Rapp, who has expertise in the area of standard setting. As an example, he recently presented a paper on the economics of standard setting at a session of the Antitrust Section of the American Bar Association, which Dr. Rapp proposed and helped to organize. (Rapp, Tr. 9770-71). 1031. Last year, Dr. Rapp presented a paper and testified about the issue of standard setting and market power at the joint hearngs of the Federal Trade Commssion and the Department of Justice on intellectual property and the knowledge based economy. (Rapp, Tr. 9771). 1032. In contrast, Complaint Counsel' s expert, Professor McMee, has no expertise in the area of standard setting. (McMee, Tr. 11345). 1033. According to the economic literature, a standard is a specification of a product design intended to achieve engineering compatibility, either between parts of a product or system or between components of a network. (Rapp, Tr. 9783). Economists recognize that standards are necessary when compatibility requirements are high and when either products, systems, or networks wil fail unless engineering compatibility is maintained. (Rapp, Tr. 9783). From an economist's point of view , standard setting does not entail specifying every detail of a product; rather, standard setting is economically effcient when it achieves compatibility but does not overdetermne product characteristics. (Rapp, Tr. 9785). 1034. Economists refer to standards that are set through formal means, i. , through a standard setting body or the governent, as de jure standards. (Rapp, Tr. 9788-89). Standards that emerge through market forces are referred to as de facto standards. (Rapp, Tr. 9789). 1035. In a market where compatibility requirements are exceedingly high, the market might permt only a single standard. (Rapp, Tr. 9791). This may occur in a network industry, which require a special kind of complementarity where systems must be able to communicate. (Rapp, Tr. 9792). The typical example of this type of network effect is the facsimile machine. A facsimile machine is worthless if it canot communicate with other facsimile machines; the more facsimile machines that it is able to communicate with, the more valuable it is. (Rapp, Tr. 9792- 93). 1036. Where compatibility requirements are less than extreme, which is more common multiple standards may coexist. (Rapp, Tr. 9791). For example, there are several standards for 152 cellular telephones, but each type of cellular telephone can communicate with the other types. (Rapp, Tr. 9791). 1037. Compatibility requirements in the DRA industry are not high. (Rapp, Tr. 9793). Although DRA must be compatible with other components in a particular computer, a computer with one type of DRA can communicate with a computer with another type of DRA. (Rapp, Tr. 9793-94). This means that network effects in the DRA industry are weak. (Rapp, Tr. 9794). 1038. Because of the weakness of network effects, different DRA standards can coexist in the market. (Rapp, Tr. 9794). 1039. Standardization by JEDEC is not necessary for marketplace success. For instance the latest generation of Video RA was not standardized by JEDEC yet gained market success. Samsung actually brought the technology to JEDEC for standardization, but JEDEC declined to adopt it. (Prince, Tr. 9021). Samsung produced the product anyway, and it became a high volume DRA product. (Prince, Tr. 9021-22). 1040. Similarly, reduced latency DRA ("RLDRA) was developed and produced by Infneon and Micron with little or no involvement by JEDEC. (Bechtelsheim, Tr. 5965-66). 1041. Standardization by JEDEC is also sometimes insuffcient for marketplace success. For example, JEDEC standardized Burst EDO, a technology brought to JEDEC by Micron (JX 23 at 68), yet it failed in the marketplace. (Wiliams, Tr. 873). Failure occurred despite the fact that Micron rigorously promoted the technology. (Wiliams, Tr. 822-24). 1042. JEDEC standardization is not always necessary nor suffcient to assure demand for a product. Standardization of SDRA by JEDEC in 1993 did not assure that there would be demand for SDRA devices (MacWillams, Tr. 4809- 10), and SDRA might never have enjoyed demand tfom the market absent Intel's developemnt of the PCI00. 1043. The publication of JEDEC' s SDRA standard was insuffcient to ensure market success or even interoperability. The JEDEC SDRA standard was not suffciently comprehensive; because of this, SDRA products made by one DRA manufacturer were not compatible with those produced by another. (MacWillams, Tr. 4908). 1044. Prompted by these incompatibilities, Intel- not JEDEC - developed the " SDRA standard in 1996. (MacWiliams, Tr. 407-09). As stated in that standard , " The objective of this document is to define a new Synchronous DRA specification ('PC SDRA' which wil remove extra functionality tfom the current JEDEC standard SDRA specification, so that it wil be a ' fully compatible ' device among all vendor designed parts. " (RX 2103- 14 at 9). 153 1045. The Intel PC SDRA specification set forth what would become the industry specification for PCI00 SDRA. (MacWiliams, Tr. 4908). For instance, Compaq used Intel PC100 SDRA compliant parts for its products. (Gross, Tr. 2350-51). Similarly, AM referred to the Intel PC SDRA specification when designing its chipsets. (polzin, Tr. 4010- 11). 1046. The Intel PC SDRA specification later set forth the industry standard for PC66 SDRA. (MacWiliams, Tr. 4908; RX 2104- 13 at 60-61). Compaq, for example, used Intel PC66 SDRA compliant parts for its products. (Gross, Tr. 2348-49). 1047. The PC133 SDRA standard was developed by yet another route. In that case DRA manufacturers and PC OEMs developed the specification. (MacWillams, Tr. 4912- 13; CX 2560 at 1). The PC133 SDRA standard was later incorporated into the Intel PC SDRA standard. (R 2104- 14 at 7 (document revision history shows addition of standards for 133MH SDRA; MacWillams, Tr. 4908). Again, Compaq used the Intel PC133 SDRA compliant DRA for its products. (Gross, Tr. 2353). 1048. Intel' s adding ofthe PC SDRA standard specifications demonstrates that there are powerfl forces in the DRA industry that affect DRA standards in a de facto rather than de jure sense. From an economic perspective, Intel can, outside of a standard setting body, create specifications or specification addendums that become the industry standard. (Rapp, Tr. 9797). Formal standard setting is therefore not the only way in which an iteration of DRA can become prominent. (Rapp, Tr. 9798). 1049. It is sometimes the case, but not always, that formal standard setting may create market power. (Rapp, Tr. 9798-99). Formal standard setting may create market power when (1) there are high compatibility requirements, (2) the standard setting body is faced with several technologies that are more or less equivalent in cost-performance terms, and (3) standard setting elevates one of those technologies above the others. (Rapp, Tr. 9799-00). Where compatibility requirements are not high and there may exist more than one standard, then little or no market power is gained through standard setting. (Rapp, Tr. 9800). 1050. Where one technology is superior to the alternatives then that technology would have been selected and become the de facto standard had the market been allowed to operate. Under these circumstances, formal standard setting does not add any market power. (Rapp, Tr. 9800-01). The market power of the technology is due to its superiority. (Rapp, Tr. 9801). 1051. Standardization of the Rambus technologies by JEDEC did not reduce the substitution possibilities of alternatives, and Rambus' s market power was unchanged by formal standard setting by JEDEC. (Rapp, Tr. 9902). 154 Rational Manufacturers and a Rational Standard Setting Organization Would Have Stil Adopted the Rambus Technologies Had Disclosure Occurred 1052. The evidence shows that the four Rambus technologies were the technologies of choice throughout the relevant time period and that a rational manufacturer or a rational JEDEC would have selected the Rambus technologies. (Rapp, Tr. 9903). The additional disclosures that Complaint Counsel allege Rambus should have made would not have affected the outcome because there were no cost-performance equivalent technologies to the two Rambus technologies incorporated in SDRA or to the four Rambus technologies incorporated in DDR. (Rapp, Tr. 9907-08). Had the allegedly required additional disclosures occurred, rational manufacturers and a rational standard setting organization would have adopted the Rambus technologies for both SDRA and DDR. (Rapp, Tr. 9908-09). 1053. It therefore follows that competition has not been adversely affected by Rambus alleged failure to disclose. (Rapp, Tr. 9908-09). It is worth noting on this issue that Complaint Counsel' s economic expert testified that the alleged conduct of Ram bus has had no impact on DRA prices, no effect on consumers, and no effect on the final PC market as of the time oftrial (over three and one-half years after Rambus began asserting its patents). (McMee, Tr. 7565-66)). 1054. The conclusion that competition has not been adversely affected by Rambus alleged failure to disclose is bolstered by the likelihood that JEDEC would have selected Rambus s four technologies had Rambus never joined JEDEC. This demonstrates that JEDEC members, acting as rational manufacturers, would have selected Ramubus s technologies, so that standardization by JEDEC did not increase Rambus s market power. (Rapp, Tr. 9863). 1055. Because the but-for world outcome is the same as the actual world outcome Rambus s alleged conduct caused it to gain no additional market power. (T eece, Tr. 10312- 13). Intel's Choice of RDRAM Conferred Market Power, Not JEDEC Standardization 1056. In the 1995- 1996 time period, Intel spent about a year exploring various alternatives for the next generation DRA. (MacWiliams, Tr. 4800-01). Intel looked at EDO SDRA, DDR, SyncLink, and Rambus. (MacWiliams, Tr. 4800-01). Other than these alternatives , " the memory vendors didn t have any other good ideas." (MacWillams, Tr. 4800- 01). 1057. An internal Intel document written by Peter MacWiliams explained that the DRA manufacturers were not focused on improving DRA technology: " (u)p to this point in time ((Q395)) memory vendors were stric(t)ly focus()ing on lowering costs and increasing density- Intel felt the memory vendors needed to get more focused on increasing access speed." (R 1532 at 1). 155 1058. Intel saw a growing performance gap in the mid- 1990' s between CPU performance and DRA performance. (R 868 at 3). Afer examnig the alternatives for a year, Intel chose RDRA to be its next generation DRA technology. (MacWiliams, Tr. 4800-01). 1059. Intel chose RDRA because of the need for higher bandwidth for use with faster CPUs and the need to satisfy memory needs driven by more I/O demands and new applications. (RX 904 at 5-6; see also RX 805 at 2 (December 1996 Intel document reciting need for increased bandwidth driven by memory intensive applications such as visual computing and noting that Intel was looking for technology beyond 100 MH SDRA). 1060. Intel' s choice ofRDRA was significant. As Richard Heye of AM - Intel's competitor in the microprocessor market - explained, in the late 1990's AM believed that RDRA would become the next volume memory product (even though the technology was revolutionary ) because it had been chosen by Intel: And given that, you know, Intel, who owns 80 percent of the market, really put his wood behind the arrow, so to speak, on Rambus, you know, they had talked about the customers, well our customers were saying, hey, you ought to use Rambus, and we talked to the memory vendors. And the memory vendors were saying, you know what, Rambus, it' s a revolutionary change, not evolutionary, but, you know, that's the way the industry is going, that's the way we re going to go, and Rambus is it. (Heye, Tr. 3685). 1061. Steve Polzin of AM testified that it was important to AM that Intel chose RDRA because Intel's selection would make RDRA a de facto standard: " (Intel) drove the volume, and if the volume DRA was Rambus, that would become the commodity part, and we had to remain competitive in terms of both performance and cost, and if the indications were most of the DRAs to be built in the world were going to be RambusDRAs, we better be compatible with them. " (polzin, Tr. 3941-42). 1062. Intel' s selection ofRDRA was also significant to the PC OEMs. For example Compaq, one of the largest producers of personal computers in the world stated in a November 1998 Compaq Memory Update that Compaq was plannng to incorporate &DRA into all Compaq products. (RX 1302 at 8). Jacquelyn Gross, the Director of Memory Procurement at Compaq (Gross, Tr. 2265), testified that Compaq was plannng to transition all of its products- 156 desktops, workstations, etc. - to RDRA at rate higher than it had ever changed memory technologies before. (Gross, Tr. 2324-27). As described in Compaq s documents, this was the (m)ost aggressive, cross divisional memory technology shift ever planned at Compaq. (RX 1302 at 8). This was planed, even though Compaq considered RDRA to revolutionary. " (Gross, Tr. 2327). 1063. Similarly, an October 1998 internal presentation reflects Compaq s sentiment at the time that "Rambus is the clear next generation memory" technology. (R 1287 at 4). As Gross explained, the reason for this belief was that Intel had told Compaq that it was going to produce chip sets for RDRA. (Gross, Tr. 2317- 18). This was important to Compaq because ninety percent of Compaq s PC applications used Intel chipsets. (Gross, Tr. 2317- 18). THE CHALLENGED CONDUCT WAS NOT EXCLUSIONARY Rambus Had a Legitimate Business Justifcation For Not Disclosing its Proprietary Patent Information 1064. Crisp was advised by Vincent, Rambus s outside patent counsel, in the 1992 time tfame, about the importance of keeping patent applications confdential. Crisp testified that Vincent "told us to not disclose our patent applications. They were confdential." Crisp understood that the consequences that might result tfom disclosure of applications included "that companies could potentially file interference actions on our patent applications in the patent offce; that in certain countries where the rules are first to file, somebody could potentially file a claim before we actually did; and that we basically would be disclosing trade secrets that could work against us in terms of our competitive position in the marketplace. " Crisp followed this advice. (Crisp, Tr. 3496). 1065. Crisp commented about Rambus s reasons not to disclose patent applications in a September 23 , 1995 email: (W)e decided that we really could not be expected to talk about potential intingement for patents that had not issued both tfom the perspective of not knowing what would wind up being acceptable to the examiner, and tfom the perspective of not disclosing our trade secrets any earlier than we are forced to. (CX 837 at 2). 1066. Respondent's economic expert , Dr. Rapp, received a bachelor s degree in economics tfom Brooklyn College in 1965, a master s degree in economic history tfom the University of Pennsylvania in 1966, and a Ph.D. in economic history tfom the University of Pennsylvania in 1970. (Rapp, Tr. 9766). He is the president ofNERA which is an economics consulting firm with five hundred employees that specializes in the economics of competition 157 including industrial economics, antitrust and intellectual property. (Rapp, Tr. 9764). He has been an economic consultant with NERA since 1977 and the president ofNERA since 1988. (Rapp, Tr. 9764). Prior to his joining NERA Dr. Rapp was a tenured professor at the State University of New York at Stony Brook. (Rapp, Tr. 9766). 1067. In addition, Dr. Rapp has published articles on predatory pricing, intellectual property economics, and innovation in high-technology markets. (Rapp, Tr. 9768-69). In the past fifteen years, a great deal of his consulting work has been in the area of high-technology antitrust and intellectual property, typically in the computer and semiconductor industries. (Rapp, Tr. 9769-70). 1068. Dr. Rapp has been qualified as an expert on numerous occasions. Since the early 1980' , Dr. Rapp has testified in hearings or trials as an antitrust economics expert, on average about once per year. (Rapp, Tr. 9771). He has testified at least five times as an expert on the economic aspects of intellectual property issues. (Rapp, Tr. 9771-72). 1069. Dr. Rapp testified that Rambus s alleged conduct was not exclusionary. (Rapp; Tr. 9921). 1070. Complaint Counsel' s economic expert, Professor McMee, did not criticize or rebut Dr. Rapp s opinion that Rambus s conduct was not exclusionary because of the presence ofa legitimate business justification. To the contrary, McMee admitted that concealing information even ifit discourages competitors tfom entering a market, is not exclusionary. (McMee Tr. 7525-27). McMee also admitted that it is not exclusionary to conceal an invention tfom competitors in order to take advantage of the invention while others cannot. (McMee, Tr. 7527- 28). 1071. Professor McMee admitted that the only "candidate purpose" he considered for Rambus s withholding information about its patent applications was monopolization, i. , he did not consider other purposes that might have led Rambus to take the risk that he identified. (McMee, Tr. 7539). 1072. The protection of trade secrets, including intentions about amending pending claims, is a valid business justification for not disclosing information regarding pending patent applications and intentions to file applications in the future. (Rapp, Tr. 9915- 16). 1073. Disclosure of trade secrets, including pending patent applications or intentions to file or amend future applications, even after a parent patent application becomes public, may: (1) jeopardize the issuance of pending claims by enabling competitors to file patent interferences or to race to be first-to-fie in certain foreign jurisdictions; and (2) result in a loss of competitive advantage by informng competitors of the firm s R&D focus or by inducing competitors to begin work around efforts earlier. (Rapp, Tr. 9916- , 9926). 158 1074. Even after the ' 898 application had been disclosed (in the form of the PCT application), Rambus stil had trade secrets (additional pending applications and intentions to file additional applications) that it could legitimately protect tfom disclosure. (Rapp, Tr. 9926). 1075. Prior to 1999, patent applications were kept strictly confdential by the PTO until patent issuance. (Fliesler, Tr. 8830). 1076. Patent applications are generally kept confdential by applicants for as long as possible. (Fliesler, Tr. 8829-30). Applicants have no enforceable rights until a patent issues and generally do not want to have their technology disclosed to competitors until such time as they do have enforceable patent rights. (Fliesler, Tr. 8829-30). In the 1990 to 1996 time tfame, if a patent ultimately did not issue tfom an application, the application would remain secret and the applicant could retain trade secret protection over the material in the application. (Fliesler Tr. 8836-37). 1077. As of October 31 , 1991 , Rambus had no trade secret protection over the written description, drawings, and original one hundred fifty claims of the ' 898 application. (Fliesler, Tr. 8894). 1078. Companies often are wary of disclosing patent applications because to do so would be to disclose to competitors the areas of technology that the company is developing and the areas of technology for which the company is seeking patent protection. (Fliesler, Tr. 8840). 1079. Even when a patent has issued tfom an original application - which results in disclosure of the drawings and written description - the applicant would stil have reasons to keep confdential other applications claiming priority back to that original application. (Fliesler Tr. 8837-38). It would be very valuable to a competitor to know what claims the applicant is actually pursuing in those other applications tfom the entirety of inventions that could be claimed based on the written description. (Fliesler, Tr. 8838, 8900-02). 1080. Similarly, even if a corresponding international patent application is published there remain business reasons for not disclosing a United States patent application, because information about the particular claims being pursued constitutes strategic business and techncal information that a company would want to keep tfom its competitors. (Fliesler, Tr. 8840- 8894-96). 1081. In addition, if information about pending applications were disclosed by a company to a competitor, the competitor could potentially slow down or interfere with the prosecution of the application. (Fliesler, Tr. 8841). The competitor could disclose prior art to the company, for example. Even if it is not relevant prior art, it could cause a dilemma for the company about whether the information triggered a duty to disclose prior art to the PTO, potentially confsing or delaying the patent prosecution. (Fliesler, Tr. 8841-42). 159 1082. The competitor could also try to provoke an "interference" at the patent offce that is, a proceeding to determine which of two applicants claiming the same invention was actually the first to invent and entitled to a patent - by claiming the same invention in one of the competitor s applications. (Fliesler, Tr. 8834- , 8842). 1083. In the United States, patents are generally awarded to the applicant who was the first to invent a given invention. (Fliesler, Tr. 8834-35). Most foreign jurisdictions, however have a first to fie rule: The first applicant to file an application that is otherwise entitled to a patent wil be awarded the patent. (Fliesler, Tr. 8838-39). Through treaties to which the United States is a party, a patent applicant has up to one year following the filing date of his US. patent application to file a corresponding application in foreign countries. Ifhe does so, the foreign country accords the application a priority date, meaning a legally effective filing date in that foreign country, of the US. application. (Fliesler, Tr. 8839-40). Whch applicant is the first to file an application in a foreign country wil be judged according to the priority date. (Fliesler, Tr. 8839-40). 1084. Martin Fliesler, a patent attorney with over thirty years of experience prosecuting patent applications, advises his clients that they should not disclose patent applications, but instead should keep them confdential. (Fliesler, Tr. 8765- , 8842-43). 1085. The need to keep patent applications confdential was well recognized in the semiconductor industry. JEDEC members were informed in 1992 of potential negative consequences flowing tfom premature disclosure of inventions. In October 1992, JC 42 Chairman Jim Townsend circulated an article entitled "Don t lose your patent rights" to members of the JC 42 commttee. (CX 342 at 8). The article advises inventors to "keep it under your hat" because disclosure of an invention may waive any rights to obtain a patent. The article states that in the United States, a disclosure made one year before filing an application can bar a patent while in some foreign jurisdictions, any disclosure before filing an application wil bar a patent. (CX 342 at 8). 1086. Rambus s keeping information about its pending or future patent applications confdential did not impose on Rambus costs or risks that were compensable only by excluding rivals and thereby gaining market power. (Rapp, Tr. 9924). 1087. These conclusions apply in the standard setting context as in any other. A company that is the member of a standard setting body may benefit tfom not disclosing information regarding its pending patent applications or its intentions to fie future patent applications regardless what standards are developed. (Rapp, Tr. 9919-20). The benefits to a company keeping control of its business and intellectual property strategies do not depend on which standard is chosen by the standard setting body. (Rapp, Tr. 9919-20). These benefits have to do with maximizing the ability to operate competitively, not standardization. (Rapp, Tr. 9920). 160 Rambus s Conduct Did Not Impact Equal or Superior Alternatives 1088. The evidence shows that Rambus s conduct was not exclusionary even as that term was defined by Complaint Counsel' s expert, Professor McMee. The exclusion of inferior products tfom the market is not exclusionary in an economic sense. (McMee, Tr. 7536). 1089. According to Professor McMee, in order for conduct to be exclusionar, it must impact equal or superior alternatives. (McMee, Tr. 7537). Professor McMee defined the phrase equal or superior alternatives to include the commercially viable alternatives that could have been chosen had Rambus disclosed. (McMee, Tr. 7762-63). 1090. Dr. Rapp testified that the cost differences that he quantified and the performance advantages of the Rambus technologies made the Rambus technologies superior to the alternatives in cost-performance terms. (Rapp, Tr. 9861-62). 1091. Professor McMee admitted that he did not quantify any cost differences between Rambus s technologies and the alternative technologies. (McMee, Tr. 11340). 1092. Although Professor McMee admitted that JEDEC members would consider the performance of alternatives in deciding whether to pursue the alternatives (McMee, Tr. 11340), he did not quantify the performance differences between Rambus s technologies and any of the alternatives he claimed were commercially viable. (McMee, Tr. 7581- , 11340). 1093. Professor McMee also admitted that JEDEC members would consider the headroom" or future flexibility of alternatives in deciding whether to pursue the alternatives. (McMee, Tr. 11340). He did not, however, compare the headroom or future flexibility of Rambus s technologies with any of the alternatives he proposed as commercially viable. (McMee, Tr. 11340-41). 1094. For example, Professor McMee admitted that JEDEC behavior and JEDEC discussions show that JEDEC members valued multiple latencies and multiple burst lengths, yet he did not quantify that value. (McMee, Tr. 11351). 1095. Professor McMee also testified that, although he had made no effort to determine if any intellectual property covered any of the alternatives that he considered commercially viable other than Kentron s technology, the presence of intellectual property could render a technology not commercially viable in his opinion, because JEDEC attached a "penalty" to the presence of intellectual property. (McMee, Tr. 7582-85). The "Commercial Viabilty" Analysis of Complaint Counsel' s Economic Expert 1096. Professor McMee testified that he believed that equal or superior alternatives were 161 excluded by Rambus s alleged conduct. His definition of "equal or superior " however, was flawed. To determne whether equal or superior alternatives were excluded, Professor McMee developed a "commercial viability" test. (McMee, Tr. 7330-31). 1097. Although he claimed that his methodology was "parallel" to standard economic tests, Professor McMee admitted that he was aware of no economic literature that describes the use of a "commercial viability" test to determine market substitutability of alternatives. (McMee Tr. 7567). 1098. According to Professor McMee, an alternative was "commercially viable" ifit constrained the price ofRambus s technologies. (McMee, Tr. 7330-31). But defined that way, the concept of "commercially viable" does not mean that the technology is "equal or superior. Even weak substitutes can constrain the price of a technology. (Rapp, Tr. 9860). An alternative can therefore be "commercially viable" in this sense without being equal or superior or even a viable alternative in any practical sense. (Teece, Tr. 10368, 10370-71). 1099. When determining whether an alternative was price constraining, Professor McMee provided no analysis of price elasticity. In other words, he did not consider the price level required before the alternatives would actually constrain the price. Instead, he simply looked for evidence that the alternative was considered as a possible alternative by members of JEDEC and that knowledgeable engineers now claimed that the alternative was viable. (McMee, lr. 7333- 34). 1100. Further, Professor McMee tied his notion of commercial viability to subjective judgments of JEDEC members (McMee, Tr. 7335) and considered the opinions of Professor Jacob (see, e. McMee, Tr. 7360) and the cost information provided by Respondent's expert Michael Geilhufe. (McMee, Tr. 11199, 11249-78). 1101. Professor McMee judged patented technologies to be "hobbling" because the JEDEC rules put a "penalty" on technologies that were covered by intellectual property. (McMee, Tr. 7337, 7582-83). He thus regarded patented technologies, such as Rambus , as inferior based on the presence of intellectual property and without regard to the level of royalties sought for that technology. 1102. In a competitive market, if the best solution in cost-performance terms is patented and involves the payment of royalties, competition wil dictate that the royalties be paid and that the patented solution is adopted. (Rapp, Tr. 9939). Whle individual executives in an industry may dislike paying royalties, just as they may dislike paying health care costs for workers or a competitive wage, they wil have no choice because competition will mandate that these costs be incurred. (Rapp, Tr. 9938-39). 1103. Professor McMee also considered "a perception of the magnitude of those problems" associated with that technology as "relevant to the determnation of which technologies 162 should be selected." (McMee, Tr. 7586). In other words, he based his determnation of whether a technology was "equal or superior" on the subjective perceptions of JEDEC members at the time, regardless of whether these perceptions were ultimately correct. Whle this factor may go to whether JEDEC would have selected the technology, it does not go to whether the alternative is equal or superior in objective terms. 1104. Professor McMee considered each company s strategic interests in which technology would be selected because of differences in techncal ability. (McMee, Tr. 7338-39). In determining whether a technology was commercially viable, he factored in whether some JEDEC members might prefer the technology because they were better equipped to produce it. Again, while this factor may go to whether JEDEC would have selected the technology, it does not go to whether the alternative is equal or superior in objective terms. 1105. Professor McMee relied on his notion of "satisficing" to conclude, in effect, that a product that has lesser performance is nonetheless "equal" to one with better performance. (McMee, Tr. 7335-36). Because he believed that JEDEC was "satisficing," Professor McMee essentially defined "equal" to include technologies that were inferior to Rambus s technologies. Professor McMee defined satisficing as referring to the process by which an organization like JEDEC wil choose an adequate solution to a problem it faces rather than expending the effort to find the perfect solution. (McMee, Tr. 7255-56). 1106. Rather than examining the actual cost differences between the Rambus technologies and the alternatives, Professor McMee opined that he had considered an amalgam of factors and determined that certain alternatives were "commercially viable" based on the information he analyzed. (See, e. McMee, Tr. 7363). Professor McMee did evaluate the alternatives using the cost information provided by Geilhufe and found that, using those cost estimates, there were a number of commercially viable alternatives to the technologies claimed by Rambus. (McMee, Tr. 11249-78). 1107. Whle Professor McMee testified that it was likely that at least one of the technologies he deemed commercially viable alternatives to Rambus s technology was equally effcient or superior to Rambus s technology, he admitted that he could not identify any particular technology as equal or superior to Rambus s technologies. (McMee, Tr. 7578-79). The Assumption by Complaint Counsel' s Economic Expert that Rambus Knowingly Assumed the Risk Of Losing Its Abilty To Enforce Its Patents 1108. In determining that Rambus s conduct was exclusionary, Professor McMee assumed that Rambus knowingly took a risk that it might lose the ability to enforce its patents by not disclosing patent interests that it did not disclose. (McMee, Tr. 7538-40). 1109. But Professor McMee admitted that Rambus would have understood that if it withheld information about its patent applications that it should have disclosed, any effort to 163 enforce its patents once they issued, would have triggered an inquiry into whether Rambus should have disclosed its patent interests. In addition, Professor McMee admitted that if a JEDEC member failed to disclose patent interests that should have been disclosed and revealed knowledge of that patent interest, e. , in a written document, the risk of a challenge that would render the patents invalid would increase substantially. (McMee, Tr. 7550). The Assumption by Complaint Counsel's Economic Expert That Rambus Violated a JEDEC Rule or Made Misrepresentations to JEDEC 1110. Professor McMee explained that Rambus s concealing of information about its patent applications would, in his opinion, be exclusionary only if it violated a rule or process. (McMee, Tr. 7530- , 7546). Professor McMee assumed that Rambus s conduct included a violation of a JEDEC rule or process. (McMee, Tr. 7530). An alternate assumption was that Rambus made misrepresentations to JEDEC. (McMee, Tr. 7478). 1111. Professor McMee assumed that Rambus "should have disclosed patents or patent applications with reference to all four of the technologies challenged in the case." (McMee Tr. 7546). But he admitted that , " (i)fthey shouldn t have disclosed on one of the technologies then my finding of exclusionar conduct on that technology is no longer - on that particular technology would no longer be reliable because I've assumed that they should have disclosed on that technology." (McMee, Tr. 7546). 1112. Professor McMee admitted that he did his analysis with no assumptions about the specific claims of any patent application that Rambus should have allegedly disclosed. (McMee Tr. 7669-70). 1113. Professor McMee also admitted that he did his analysis with no assumptions about the specific date that Rambus allegedly should have made the disclosures that Complaint Counsel allege should have been made. (McMee, Tr. 7671). 1114. Professor McMee also admitted that he did his analysis with no assumed specific triggering event that would have caused Rambus to be obligated to make disclosures to JEDEC. (McMee, Tr. 7671). 1115. Professor McMee admitted that if work on DDR had not begun by the time Rambus had left JEDEC and ifthere was no duty to disclose absent such work, the conclusions that he drew tfom assuming that Rambus failed to disclose with regard to DDR would fall away. (McMee, Tr. 7575). 1116. Professor McMee admitted that ifRambus had made the additional disclosures that Complaint Counsel allege should have been made, JEDEC ignored the disclosure, and JEDEC incorporated the Rambus technology nonetheless, Rambus would not have engaged in exclusionary conduct. (McMee, Tr. 7682). 164 1117. Professor McMee also admitted that there are situations in which JEDEC could become aware ofRambus s potential patents other than through Rambus s disclosure of that information to JEDEC, such that Rambus s failure to disclose would not, as a matter of economics, constitute exclusionary conduct. (McMee, Tr. 7686). 1118. Professor McMee further admitted that it is plausible with his assumptions that if Rambus never joined JEDEC, JEDEC would have selected the four Rambus technologies for inclusion in its standards. (McMee, Tr. 7688). The Economic Evidence Regarding "Hold Up" and Disclosure Costs 1119. Professor McMee based his analysis that Rambus' s conduct was exclusionary on several assumptions, one of which was the assumption that Rambus s conduct violated a JEDEC rule or process. (McMee, Tr. 7530-31). 1120. Professor McMee admitted that he had done no analysis to determine whether JEDEC' s rules and processes advanced the interests of antitrust law. (McMee, Tr. 7532-33). 1121. Nor did Professor McMee perform any analysis of JEDEC' s costs and benefits in order to determne the economically effcient disclosure rules for it to impose. (McMee Tr. 7727). In fact, he admitted that he has not investigated the economic effciency ofJEDEC' rules. (McMee, Tr. 7727-28). 1122. As an economic matter it is disputed whether the optimal time for disclosure of information regarding patent interests is as early in the standardization process as possible. (Teece, Tr. 10385). As Professor Teece testified, disclosure involves costs, so the optimal time for disclosure must consider those costs. (Teece, Tr. 10385). Depending on the costs and benefits, later disclosure may be optimal. (Teece, Tr. 10402). 1123. The costs of disclosure include the cost to the patent applicant of losing trade secrets and confdentiality. (Teece, Tr. 10453). The costs to the standard setting organization are that it must try to evaluate and assess the highly preliminary information regarding the patent application. (Teece, Tr. 10453-54). 1124. Since patents are not going to change and are public, the costs associated with disclosing patents are less than those associated with disclosing patent applications. (Teece Tr. 10454-55). 1125. The narrower the scope of disclosure regarding patent applications, the lower the costs and burdens of disclosure. (Teece, Tr. 10454, 10547-58). Ifintellectual property issues are put aside once a RA assurance is given, there is less need for disclosure. (Teece, Tr. 10548). 165 1126. Professor McMee admitted that JEDEC' s disclosure rules do little to mitigate risk of hold up because the disclosure obligation applies only to the knowledge of the representative at the meeting, rather than that ofthe member company (McMee, Tr. 7724) and because, in large companies, the representative might not have a lot of knowledge about the company s patents. (McMee, Tr. 7724-25). 1127. Professor McMee also admitted that a JEDEC disclosure requirement would not mitigate the risk that the standard might involve technology covered by patents held by nonmembers. (McMee, Tr. 7725). XI. THE EVIENCE DOES NOT SUPPORT COMPLAINT COUNSEL'S ARGUMENT THAT THERE WERE VIBLE ALTERNATIVS TO RAMBUS' TECHNOLOGIES The Testimony of Professor Jacob Regarding Allegedly Viable Alternatives Is Not Persuasive 1128. Complaint Counsel' s expert witness regarding viable alternatives, Professor Jacob has never done DRA circuit design. (Jacob, Tr. 5588). Indeed, Professor Jacob had never designed any circuits for computer chips (even apart tfom DRAs) that were to be fabricated prior to 2002. (Jacob, Tr. 5588). Aside tfom reviewing some DRA data sheets Professor Jacob, who was a student at the time, had no particular DRA-related experience in the mid- 1990' s. (Jacob, Tr. 11148). Professor Jacob did not obtain his graduate degree and begin to teach electrical engineering until 1997. (Jacob, Tr. 5357). 1129. By contrast, Respondent' s techncal experts have a wealth of relevant experience in the DRA and semiconductor industries. Dr. Soderman was employed in the semiconductor industry for over thirty years during which time he designed DRAs as well as various other types of integrated circuits. (Soderman, Tr. 9329-36). 1130. Likewise, Michael Geilhufe worked in the semiconductor industry for over thirty years. (Geilhufe, Tr. 9543-52). Geilhufe holds four patents for DRA design and managed Intel' s international manufacturing operations which involved working closely with DRA manufacturers such as Samsung. (Gelhufe, Tr. 9549- , 9553). 1131. In Professor Jacob' s publications comparing certain DRA architectures, he tried to model their performance as precisely as possible using software simulation. In contrast Professor Jacob did no such software simulation with respect to the alternatives that he proposed to Rambus s technology. (Jacob, Tr. 5589). 1132. With the exception of three of his alternatives (using a burst terminate command increasing the number of pins on the DRA, and increasing the number of pins on the module), Professor Jacob did no simulation or modeling of any kind to try to assess the alternatives 166 performance. (Jacob, Tr. 5590-91). 1133. Professor Jacob' s proposed alternatives were not suffciently detailed to enable an actual circuit design. (Geilhufe, Tr. 9673). 1134. Professor Jacob did not do any investigation to determne whether any of his proposed alternatives were covered by patents owned by Rambus or others. (Jacob, Tr. 5601). Complaint Counsel Did Not Prove That There Were Viable Alternatives to the Rambus Technologies Adopted in the SDRAM Programmable CAS Latency 1135. Complaint Counsel have suggested, through their techncal expert, Professor Jacob the following possible alternatives to programmable CAS latency in SDRAs: (1) (2) (3) (4) (5) (6) Use fixed CAS latency parts; Program CAS latency by blowing fuses on the DRA; Scale CAS latency with clock tfequency; Use dedicated pins to transmit latency information tfom the controller to the DRA; Explicitly identify CAS latency in the read command; Stay with an asynchronous-style DRA. (Jacob, Tr. 5370-96). Complaint Counsel Did Not Prove That the Use of Fixed CAS Latency Parts Was a Viable Alternative 1136. One of the alternatives proposed by Professor Jacob for programmable CAS latency was to fix the CAS latency at the design stage, the manufacturing stage, or the packaging stage. (Jacob, Tr. 5371). Fixing CAS latency at the design stage would result in a single part with only one CAS latency. (Jacob, Tr. 5373). Fixing CAS latency at the processing stage would involve a "metal mask option" that would fix the CAS latency to one value or another. (Jacob, Tr. 5373-75). Fixing CAS latency during packaging would require a multiplexer that would be hardwired to either power or ground during the packaging process to select one of two latency values. (Jacob, Tr. 5375-76). 167 1137. Multiple CAS latency values are required for SDRAs because users of DRAs would prefer to buy parts that they can insert in a variety of systems with different bus speeds. (R 1626 at 3-4; Soderman, Tr. 9346-47). The appropriate CAS latency for a part wil depend on the bus speed and the access time of the DRA. (Soderman, Tr. 9347-48). Therefore, using fixed latency parts would require multiple fixed latency parts, as opposed to a single programmable latency part. (Soderman, Tr. 9347-48). 1138. Mark Kellogg of IBM testified that, in the 1992 time tfame , " we weren t convinced that we knew the right latency and we did expect that the DRA tfequency would go up over time - that we knew the correct latency if we were to select one and we expected that the DRA tfequency would increase over time, which meant we might wish to change the CAS latency. (Kellogg, Tr. 5139). 1139. The mode register in SDRAs and DDR SDRAs reserves three bits for CAS latency, allowing for up to eight different CAS latency values. (CX 234 at 150). 1140. Release 4 of JEDEC Standard 21-C (November 1993), which contains the first published SDRA standard, specified three required CAS latency values (1, , and 3) and one optional CAS latency value (4). (JX 56 at 114; Lee, Tr. 11003-04). Release 9 ofJEDEC Standard 21-C (August 1999), which contains the first published DDR SDRA standard specified two required CAS latency values for SDRAs (2 and 3) and one optional value (4); also specified two required CAS latency values for DDR SDRAs (2 and 2. 5) and three optional values (1.5 , and 3. 5). (CX 234 at 150; Lee, Tr. 11068-72). 1141. Although not all of the eight possible values of CAS latency are used in SDRAs and DDR SDRAs, the other possibilities were reserved to preserve flexibility for future additions. (Lee, Tr. 11072-73). 1142. Desi Rhoden gave a presentation on "Future SDRA at the March 1996 meeting of the JEDEC 42. 3 subcommttee. (JX 31 at 64; Rhoden, Tr. 489-90). The presentation indicates that CAS latencies of2, 3 , 4, 5 and 6 would be required for different generations of SDRAs. (JX 31 at 64; Rhoden, Tr. 490-91). 1143. JEDEC' s DDR2 SDRA standard intends to expand the use of programmable latency. (Soderman, Tr. 9351-53). Preliminary DDR2 SDRA data sheets tfom both Hynix and Samsung indicate that DDR2 SDRAs wil continue to have three bits in the mode register reserved for CAS latency, allowing for up to eight different CAS latency values. (R 2099- 14 at 21; RX 2099-39 at 20; Soderman, Tr. 9351). Hynix s part provides three different CAS latency values (3 , 5). (R 2099- 14 at 21; RX 2099-39 at 20; Soderman, Tr. 9351). 1144. DDR2 SDRAs also reserve three bits in an "extended mode register" for additive latency, " allowing for up to eight different additive latency values. (R 2099- 14 at 24; RX 2099-39 at 22; Soderman, Tr. 9351-53; Lee, Tr. 11068). Hynix s part provides six different 168 additive latency values (0, 1 , 3 , 4, and 5), while Samsung s part provides five different additive latency values (0, 1 3 and 4). (RX 2099- 14 at 24; RX 2099-39 at 22; Soderman, Tr. 9351- 53; Lee, Tr. 11068). The "read latency" in DDR2 SDRAs (that is, the number of clock cycles tfom receipt of a CAS command until data is output onto the bus) is the sum of the CAS latency and the additive latency. (RX 2099- 14 at 32; RX 2099-39 at 37). 1145. In 1993 , Micron s first SDRA design allowed for four different CAS latencies (1, , 3 , and 4). (Lee, Tr. 11063-64). 1146. Micron currently sells an SDRA for the graphics market allowing for three different CAS latencies (1, , and 3). (Lee, Tr. 11064-67). 1147. The total unit cost for a mature product built by a first tier DRA manufacturer in the mid- 1990' s was approximately two dollars. (Geilhufe, Tr. 9564). Multiple fixed latency parts would have been an expensive alternative, for several reasons. (Soderman, Tr. 9348-49). 1148. First, manufacturing multiple fixed latency parts would decrease a DRA manufacturer s yield due to speed distribution. (Soderman, Tr. 9348; Geilhufe, Tr. 9577). DRAs cannot be accurately tested for speed until after packaging; fixing the CAS latency prior to that time would result in some parts that are not capable of performing at the CAS latency that has been fixed and, therefore, would not be usable. (Soderman, Tr. 9347-49; Geilhufe, Tr. 9577- 78). If CAS latency were programmable, those slower parts would be usable at a higher CAS latency value. (Soderman, Tr. 9347-49; Geilhufe, Tr. 9577-78). 1149. Second, fixing CAS latency would result in DRA manufacturers losing some of the price premium associated with their fastest (i. , lowest CAS latency) parts which can sell for fifty percent or more over their standard parts. (Soderman, Tr. 9348-50; Lee, Tr. 11074-75). This, again, is because the latency would be fixed prior to accurate speed testing and consequently, some parts that would be capable offaster performance (i. , operating at a low CAS latency) wil be set to a CAS latency higher than necessary. (Soderman, Tr. 9348-50; Lee Tr. 11074-75). 1150. Steve Polzin of AM testified that "Fixed CAS latency would have been pretty onerous for the DRA manufacturers" and "would have a significant cost impact for the DRA manufacturers." (polzin, Tr. 3992). 1151. Joe Macri of A TI testified that t l (Macri, Tr. 4762 (in camera)). l (Macri, Tr. 4762-63 (in camera)). 169 1152. Third, there would have been an increase in design, photo tooling, and qualification costs because multiple products would have had to be designed and manufactured, rather than just one product. (Geilhufe, Tr. 9679 9682- 9690). 1153. Some design effort would have been required for each different CAS latency; one mask would have had to be changed for each different CAS latency; and each different CAS latency part would have had to be qualified before it could be sold. (Geilhufe, Tr. 9575- , 9578- 79). 1154. Fourth, multiple fixed latency parts in place of a single programmable latency part would result in substantial inventory costs. (Soderman, Tr. 9349-50). 1155. Gordon Kelley of IBM testified about the benefits of programmability as follows: One of the advantages of that is that that drives low cost. The producer does not have to maintain multiple part numbers. One part number fits many applications. That' s one ofthe drivers to low cost." (G. Kelley, Tr. 2550-51). 1156. When first developing the Rambus technology, Drs. Farmwald and Horowitz considered having a fixed latency. (Horowitz, Tr. 8532). Dr. Horowitz learned tfom an early visit to a DRA manufacturer the importance of having a single, as opposed to multiple parts. At that time, there were two different packages for DRAs, and the DRA manufacturer was making a single die that could fit into either package even though this entailed ten percent additional die area. (Horowitz, Tr. 8532-33). Dr. Horowitz s understanding at the time was that the reason for making a single part despite the die size penalty was that inventory costs tfom having two different designs during the manufacturing process would be too expensive. (Horowitz, Tr. 8533-34). 1157. Multiple fixed latency parts would also be inferior tfom the user s standpoint. Because the part could no longer be programmed to operate in various systems, a user would have to pay attention to the part' s detailed specifications to determine whether it would work in its system. (Soderman, Tr. 9350-51). 1158. In an April 11 , 2000 email responding to a proposal to fix CAS latency in DDR2 Bill Hovis of IBM rejected the idea, both because of cost concerns and because ofthe benefits to DRA users tfom programmable CAS latency. (R 1626 at 3). 1159. Using fixed latency would not allow for the elimination of the mode register in SDRAs and DDR SDRAs because the mode register is used for purposes other than programmng CAS latency. In the JEDEC SDRA standard, the mode register is used for storing CAS latency, burst length and burst type. (CX 234 at 150). Certain SDRAs being manufactured use the mode register for additional purposes as well, such as for programmng operating mode and wrte burst mode. (R 2100- 13 at 3). The DDR SDRA standard adds an extended mode register used to enable or disable a DLL. (CX 234 at 176). The DDR2 SDRA 170 standard expands the use of the mode register even further, with the mode register being used to program burst length, burst type, CAS latency, test mode, DLL reset, and tWR and the extended mode register being used to program DLL enable, output driver impedance control, RTT, additive latency, OCD, /DQS enable and RDQS enable. (R 2099- 14 at 21 24; RX 2099-39 at 20 22). 1160. Although there would have been a decrease in testing costs because each part would have had to be tested for a single CAS latency, rather than for multiple CAS latencies (Geilhufe, Tr. 9576), this cost saving would have been far outweighed by the cost increases due to other factors. 1161. The fixed CAS latency alternative would have resulted in the following approximate net costs compared to the cost of SDRA in the mid- 1990' , assuming a first-tier DRA manufacturer and a product that is already well down the learnng curve with a volume of twenty millon unit volume, that is, a product that has already realized its cost improvement: $100 000 increase in product design costs per latency; $50 000 increase in photo tooling costs per latency; one cent decrease per unit in testing costs at wafer sort; three cents per unit cost increase due to reduced good die yield; two cents per unit increase in inventory costs; and $250 000 increase in qualification costs per latency. (Geilhufe, Tr. 9562- , 9575-79). 1162. The net increase in variable costs for the fixed CAS latency alternative is, therefore approximately four cents per unit. The total cost increase is approximately six cents per unit calculated by converting the fixed costs to per unit costs through division by twenty millon (the unit production run) and adding the resulting per unit fixed costs to the per unit variable costs. (Geilhufe, Tr. 9579). 1163.. The additional inventory cost estimate is based on three different fixed latency parts being manufactured, the number of required CAS latencies in the original SDRA standard instead of a single programmable latency part. (Geilhufe, Tr. 9578; JX 56 at 114). 1164. The estimate for increased inventory costs is conservative, because inventory costs due to multiple products can be much larger. For example, in 1989, Apple Computer reported $27 millon quarterly loss attributed entirely to purchasing a DRA part that they could no longer use in their systems. (Geilhufe, Tr. 9587). This amounted to a loss of about five to six dollars per unit. (Geilhufe, Tr. 9588). Complaint Counsel Did Not Prove That Programming CAS Latency with Fuses Was a Viable Alternative 1165. Professor Jacob' s proposed alternative of programmng CAS latency with fuses is similar to his fixed CAS latency alternative because, once the fuse is blown, the part has a fixed CAS latency. (Jacob, Tr. 5378-79). 1166. Fuses can be blown by lasers or electrically. (Jacob, Tr. 5380). 171 1167. Laser-blown fuses are more reliable than electrically-blown fuses. (Soderman Tr. 9356-57; Geilhufe, Tr. 9581-82 (Certain products using electrically blown fuses were discontinued at Intel for reliability reasons. )). 1168. In the 1995 time trame, the dominant fuse technology used by major DRA manufacturers was laser fuse technology. (Geilhufe, Tr. 9581-82). There are DRA manufacturers who do not have the technology to blow fuses electrically and did not have such technology in the 1995-2000 time trame. (Jacob, Tr. 5596; Geilhufe, Tr. 9740-41). 1169. Fixing the CAS latency with laser-blown fuses prior to packaging would lead to the same logistical diffculties as Professor Jacob' s fixed CAS latency alternative. (Soderman Tr. 9354). 1170. Another disadvantage of using fuses is that the manufacturer would have to blow the fuses after receiving orders for parts, leading to a "time lag trom request to delivery of parts. (Kellogg, Tr. 5131). 1171. Laser blown fuses could not be blown by OEMs (original equipment manufacturers) because they cannot be blown after packaging. (Jacob, Tr. 5378-80; Soderman Tr. 9354-56). Electrically-blown fuses can be blown after packaging, but they stil could not be blown by OEMs because the part must be tested after the fuse is blown to make sure it is operating correctly. (Soderman, Tr. 9517). OEMs do not have the capability to perform such testing. (Soderman, Tr. 9354-56). 1172. There would have been an increase in design costs due to the design effort to provide the fuses required. (Geilhufe, Tr. 9575, 9584-85). 1173. There would have been an increase in testing costs due to the time required to blow a fuse and perform certain additional steps. (Geilhufe, Tr. 9585). 1174. There would have been reduced good die yield, inventory, and qualification costs of the same magnitude as the corresponding increases for the fixed CAS latency alternative because, once the fuse is blown, the part is a fixed latency part. (Geilhufe, Tr. 9585-89). 1175. Programmng CAS latency by blowing fuses would have resulted in the following approximate net costs compared to SDRA in the mid- 1990' , assuming a first-tier DRA manufacturer using existing laser fuse technology and a product that is already well down the learnng curve with a volume of twenty millon unit volume, that is, a product that has already realized its cost improvement: $100 000 increaSe in product design costs per latency; one cent increase per unit in testing costs at wafer sort; three cents per unit cost increase due to reduced good die yield; two cents per unit increase in inventory costs; and $250 000 increase in qualification costs per latency. (Geilhufe, Tr. 9562- , 9584- , 9589). 172 1176. The net increase in variable costs for the alternative of programmng CAS latency by blowing fuses is, therefore, approximately six cents per unit. The total cost increase is approximately seven cents per unit, calculated by converting the fixed costs to per unit costs through division by twenty millon (the unit production run) and adding the resulting per unit fixed costs to the per unit variable costs. (Geilhufe, Tr. 9589). 1177. If the DRA manufacturer did not have antifuse or electrically blown fuse technology available and wished to use that technology, adding it to the manufacturing process would entail several millon dollars in additional development costs. (Geilhufe, Tr. 9583-84). Complaint Counsel Did Not Prove That Scaling CAS Latency With Clock Frequency Was a Viable Alternative 1178. Professor Jacob' s proposed alternative of scaling CAS latency with clock trequency involves having the DRA either being informed of the trequency by the memory controller or using some sort of internal circuitry to sense the trequency. The DRA would then calculate the appropriate CAS latency to use based upon its own inherent latency. (Jacob, Tr. 5383). 1179. Professor McMee did not testify that this alternative was commercially viable. (McMee, Tr. 7363). 1180. Having the controller send the bus speed information to the DRA would require extra pins and circuitry on the controller and, potentially, extra pins on the DRA, adding manufacturing expense. (Soderman, Tr. 9359-60). 1181. Having the DRA sense the bus speed would require complex and costly circuitry on the DRA. (Soderman, Tr. 9358). 1182. Scaling CAS latency with clock trequency is not an alternative to using a register to store a latency value because the latency value would stil have to be stored in a register potentially violating Rambus s patents. (R 1626 at 2; Soderman, Tr. 9359). 1183. For example, upon a formal intingement analysis, this alternative might be determined to be covered by claim 1 of US. Patent No. 5 953 263 , assigned to Rambus. (CX 1517 at 29). 1184. Scaling CAS latency with clock trequency was actually proposed by Micron as an alternative to programmable CAS latency for DDR2. At the March 2000 meeting of the JEDEC JC 42. 3 subcommttee, Micron made a first showing entitled "Simplifying Read Latency for DDRII." (CX 154A at 9 25-32). In its presentation, Micron noted that one approach would be to "offer devices with a fixed read latency." (CX 154A at 26). Under this approach , " (v)endors 173 can offer different speed devices, each with a different fixed latency, " but there would be the (d)isadvantage" that " (u)sers may need to order different parts to cover different applications. (CX 154A at 26). 1185. Micron went on to present a second approach, proposing to scale CAS latency with clock trequency: "offer devices with programmable operating trequency; each operating trequency range has a fixed read latency associated with it." (CX 154A at 27). 1186. In an email dated April 13 , 2000 trom Mark Kellogg of IBM to Ar Kilmer of IBM Kellogg discussed the proposals made by Micron at the March 2000 JEDEC meeting in the context of the Rambus patents. (RX 1626 at 2). Kellogg noted that " (i)n the last JEDEC meeting, the option of a single latency device was pooh-poohed." (R 1626 at 2). Kellogg went on to discuss Micron s alternative proposal of scaling CAS latency with clock trequency. Kellogg stated: (T)he alternate proposal trom Micron (programmng the trequency range instead of CAS Latency) was better-received. The problem with the latter proposal (in my mind), was that nothing changed except the name assigned to the command register bits (originally defined as CAS Latency, now to be defined as trequency range or something similar). As such, I felt they were walking a fine line and that this change would not hold up in court as being anything other than an attempt to circumvent possible patent intingement via a term redefinition. (RX 1626 at 2). Complaint Counsel Did Not Prove That Using Dedicated Pins to Identify the Latency Was a Viable Alternative 1187. Professor Jacob' s proposed alternative of using an existing or dedicated pin to identify the latency involves a pin on the DRA that would select one CAS latency if it received a high voltage and a different CAS latency if it received a low voltage. (Jacob, Tr. 5386-87). 1188. This alternative would require additional wiring in the DIM and trom the DIM to the memory controller. These additional wires can have a "noise glitch" - that is, the signals could be perturbed by adjacent signals - that would upset the CAS latency value and lead to improper operation of the DRA. (Soderman, Tr. 9361-62). 1189. Certain confgurations ofSDRAs had no "no-connect" pins. (CX 234 at 84; Geilhufe, Tr. 9741-42). Certain others had only a single "no-connect" pin. (RX 2100- 13 at 1; Polzin, Tr. 4026-28). 174 1190. Moreover, pins designated as "no connect" are not necessarily available for other uses because they may be used in testing. (Soderman, Tr. 9463-65). 1191. Pins designated as "no connect" also may be unavailable because they are reserved for uses in other confgurations. For example, if a manufacturer used the same mask for x4, x8 and x16 confgurations, and if a pin designated "no connect" in the x4 and x8 confgurations was used as a data pin in the x16 confguration, that pin could not be used for other purposes in the x4 and x8 confgurations; in other words, the pin would need to remain a "no connect" pin in the x4 and x8 confgurations. (Lee, Tr. 11084-87). 1192. Pins designated as "no connect" may also be valuable for use in future, higher density generations of the product. As Gordon Kelley of IBM testified, using up a pin is not something that was done "easily, because once you use that pin up for a function, you don t have it available to you in the future for generation advance. As the memory densities increase, we need pins for more addressing of more address locations and those pins are very valuable for that feature, so this would have limited the number of generations of DRA design that we could have used if we were to use up this pin. (1. Kelly, Tr. 2552-53). 1193. To achieve the same level of flexibility as SDRAs and DDR SDRAs which have three bits in the mode register for storing a CAS latency value, a manufacturer would have to add three pins to a DRA with no pins available. (Soderman, Tr. 9362; Geilhufe, Tr. 9589- 90). Moreover, since the packages in use in the 1990' s were all rectangular and required pins to be added in multiples of two, four pins would have to be added. (Soderman, Tr. 9362-63; Geilhufe, Tr. 9590). 1194. In its license negotiations with Rambus in 1994, Samsung was motivated to seek a non-assertion provision for non-Rambus-compatible uses ofRambus s inventions because ofthe on-chip DLL shown in Rambus s PCT application. (CX 2078 at 107-08 (Karp, Micron Dep. )). 1195. The number of pins required could not be reduced by having more than two voltage levels per pin. Although Professor Jacob has suggested that this could be done, he has never designed a circuit that would detect more than two voltage levels at high trequency. (Jacob Tr. 11126). No SDRA or DDR SDRA parts support more than two voltage levels per pin in normal operation. (Jacob, Tr. 11125-26). Having more than two voltage levels on a pin would require sophisticated circuitry that would be easily perturbed by noise. (Soderman, Tr. 9363-64). 1196. The first Rambus DRA, the 4. 5 megabit part built by Toshiba in the early 1990' had a pin with three voltage levels. (Horowitz, Tr. 8549). Rambus did not want to use an extra pin for entering test mode and, instead, created an extra voltage level on one of the existing pins for that purpose. (Horowitz, Tr. 8549). Although Rambus believed that the part had been built 175 and designed with enough separation between the voltage levels to prevent confsion, in fact the part sometimes failed because it entered test mode accidentally. (Horowitz, Tr. 8550-51). Rambus never used a pin with more than two voltage levels on subsequent Rambus DRAs. (Horowitz, Tr. 8551). 1197. Assuming a first-tier DRA manufacturer and a product that is already well down the learnng curve with a volume of twenty millon unit volume, that is, a product that has already realized its cost improvement, programmng CAS latency by using dedicated pins would have resulted in approximately four cents in increased packaging costs per unit, compared to the cost ofSDRAs in the mid- 1990' , because of the need for additional four pins. (Geilhufe, Tr. 9562- , 9589-91). 1198. The four cent increase cost estimate for this alternative is very conservative. First standard packages generally add more than four pins - for example, the JEDEC SDRA standards move from a 44-pin package to a 54-pin package, adding ten pins, and then to a 66-pin package, adding twelve pins. (Geilhufe, Tr. 9590; CX 234 at 99- 106). Thus, if there were not enough pins available on a certain standard package, one might have to move up to the next standard package, adding many more than the bare minimum of four pins. 1199. Second, in addition to the four pins on the DRA, more pins would also be required on the memory controller; however, every pin on controllers is fully utilized, so pins would have to be added there. (Soderman, Tr. 9363; Geilhufe, Tr. 9591). 1200. Third, both a new, more expensive connector may be required to connect the DIM to the motherboard, and more lines on the bus. (Geilhufe, Tr. 9590-91). Complaint Counsel Did Not Prove That Identifying CAS Latency in the Read Command Was a Viable Alternative 1201. Professor Jacob' s proposed alternative of identifying CAS latency in the read command would involve a different command sent tfom the controller to the DRA for each desired CAS latency. (Jacob, Tr. 5389). 1202. However, this alternative, upon a formal intingement analysis, might be determined to be covered by claim 1 of US. Patent No. 5 953 263 , assigned to Rambus. (CX 1517 at 29). 1203. Professor Jacob testified that this alternative would not require a register because a latch" could be used to store the latency information instead. (Jacob, Tr. 5393). This distinction is of no consequence because a register is a generic class of storage (Soderman, Tr. 9450-51), and one type of register is a latch. (Soderman, Tr. 9450-51; Horowitz, Tr. 8508-09). 1204. Professor Jacob concedes that "a register might be built out oflatches." (Jacob 176 Tr. 5393). He testified that: "A latch is a specific implementation. A register implies how a piece of storage is being used." (Jacob, Tr. 5393). 1205. Identifyng CAS latency in the command would have the negative side effect of limiting the simultaneous issuing of independent commands that is possible with the current command set. (Jacob, Tr. 5599). 1206. This alternative might also be covered by US. Patent No. 5 835 956, which is assigned to Samsung and was not considered by Professor Jacob. (RX 1308; Jacob, Tr. 5599- 601). Claim 1 of that patent claims a synchronous memory device that is capable of receiving latency mode information and selecting one of a plurality of latency modes in response to the information. (R 1308 at 90). Complaint Counsel Did Not Prove That Staying with Asynchronous Technology Was a Viable Alternative 1207. SDRA, SLDRA and RDRA are all synchronous designs. (Jacob, Tr. 5601- 02). 1208. Despite the success of SDRA, a substantial amount of work on asynchronous technology has continued during the last decade at both the academic and commercial levels. (Jacob, Tr. 5602; Horowitz, Tr. 8560-61). 1209. When Dr. Horowitz began working on what was to become RDRA, he had substantial experience in asynchronous designs. Some of Dr. Horowitz s Ph.D. students had done their dissertations in asynchronous design, and Dr. Horowitz had himself done studies comparing asynchronous to synchronous designs. (Horowitz, Tr. 8559). 1210. Dr. Horowitz decided that a synchronous design would be necessary for RDRA because he did not believe that one could build a very high-performance asynchronous interface. (Horowitz, Tr. 8498). As a circuit designer, Dr. Horowitz realized that when a signal passes through a block of circuitry, the amount by which it is delayed is subject to some uncertainty because of fluctuations in certain parameters such as temperature and voltage. (Horowitz Tr. 8499-00). In the absence of a timing reference, like the clock in a synchronous system, as the signal continues to travel through more and more blocks, the amount of uncertainty will grow so that it will not be possible to predict with any accuracy when data will arrive. (Horowitz, Tr. 9499-00). For high performance, the amount of uncertainty must be kept to a small, predictable amount; this requires a synchronous system. (Horowitz, Tr. 8501-02). 1211. Asynchronous memories are very dependent on loading on the bus - that is, how many other chips are on the bus. In a general purpose environment, the loading of the bus can vary; consequently, asynchronous memories do not perform well in a bus environment at high tfequencies. (Soderman, Tr. 9366). 177 1212. It was generally understood in the 1990's that asynchronous memories were not capable of reaching the speeds that would be required for future DRAs. For example, an article by a Fujitsu engineer published in 1996 states that "(a) synchronous DRAs, be that EDO or Burst EDO, can not keep up with bus speeds of over 66 MH." (R 2099-4 at 4). Jacquelyn Gross of Hewlett-Packard, formerly of Compaq, testified that it was Compaq s view in the 1996- 1997 time tfame that asynchronous technology was limited in the bandwidth it could achieve and that synchronous technology "provided higher benefits." (Gross, Tr. 2347). Steve Polzin of AM testified that in the 1996- 1997 time tfame it was his opinion that, due to inherent limitations, asynchronous technology had less "headroom " that is less of an ability to offer improved performance over time, than synchronous technology. (polzin, Tr. 4033-35). 1213. Burst EDO was an asynchronous type of DRA that Micron was strongly pushing in the mid- 1990' s. (Wiliams, Tr. 822- , 879). A 1995 Micron publication entitled "The Burst EDO DRA Advantage" raises a question about the viability of Burst EDO ("BEDO") at bus speeds greater than 75 MH and states that "BEDO wil probably reach its limit somewhere around 100 MH." (CX 2632 at 5). 1214. Burst EDO was standardized by JEDEC in March 1995. (Wiliams, Tr. 873 879- 80; RX 585 at 1). However, Burst EDO failed in the marketplace in competition with SDRA. (Wiliams, Tr. 829). Programmable Burst Length 1215. Complaint Counsel, through Professor Jacob, have suggested the following possible alternatives to programmable burst length in SDRAs: Use fixed burst length parts; (1) (2) Program burst length by blowing fuses on the DRA; (3) Use dedicated pins to transmit burst length information tfom the controller to the DRA; Explicitly identify burst length in the read command; (4) (5) Use a burst termnate command; (6) Use a CAS pulse to control data output. (Jacob, Tr. 5397- 12). 178 Complaint Counsel Did Not Prove That the Use of Fixed Burst Length Parts Was a Viable Alternative 1216. Professor Jacob' s proposed alternative of using fixed burst length pars, similar to his fixed CAS latency alternative, involves fixing the burst length of the DRA during the design phase, manufacturing phase, or packaging phase. (See Jacob, Tr. 5373 , 5397-98) 1217. Different burst lengths are required for different applications, so multiple fixed burst length parts would be required for this alternative. (Soderman, Tr. 9368-69). As Gordon Kelley of IBM testified with respect to programmable burst length: The programmable feature allowing you to make that selection when the PC or the computer powered up was a nice feature because it allowed you to use devices that were common tfom multiple suppliers, put them into many different types of machines. Some of them would be a burst length of one, some would be a burst length of four, with the same part that was programmed at power-up. One of the advantages of that is that that drives low cost. The producer does not have to maintain multiple part numbers. One par number fits many applications. That's one of the drives to low cost. (G. Kelley, Tr. 2550-51). 1218. The mode register in SDRAs and DDR SDRAs reserves three bits for burst length, allowing for up to eight different burst length values. (CX 234 at 150). 1219. Release 4 ofJEDEC Standard 21-C (November 1993), which contains the first published SDRA standard, provided specified two required burst length values (4 and 8) and three optional burst length values (1, , and full page). (JX 56 at 114). Release 9 ofJEDEC Standard 21-C (August 1999), which contains the first published DDR SDRA standard specified three required burst length values for SDRAs (2 , and 8) and two optional values (1 and full page); it also specified three required burst length values for DDR SDRAs (2 , and 8). (CX 234 at 150). 1220. Burst lengths of one are used in graphics applications. (Lee, Tr. 11076). 1221. Micron sells SDRAs that allow for five different burst lengths (1, , 8 and full page). (RX 2100- 13 at 1; Lee, Tr. 11078-80). 1222. Mark Kellogg of IBM noted that a disadvantage of fixing burst length in the manufacturing process would be that if a manufacturer did not have enough parts of the right 179 burst length in stock, there could be a time lag of two weeks to one month before parts could be delivered. (Kellogg, Tr. 5119). Kellogg recommended to his company in 1992 that they support the programmable burst length feature because " (i)t offered us the greatest flexibility. We had a lot of applications. " (Kellogg, Tr. 5132). 1223. A fixed burst length would have been "very, very bad for AM." (polzin Tr. 3994). AM designed processors to use a burst length of eight "for performance reasons but because Intel processors use a burst length offour, fixing burst length would have meant that manufacturers would most likely produce burst length of four parts. (polzin, Tr. 3994). 1224. JEDEC originally intended to fix the burst length at four in the DDR2 SDRA standard. (Soderman, Tr. 9369; Macri, Tr. 4673-74). Afer further review by the DRA manufacturers and the user community, it was determined that programmable burst length needed to be retained. (Soderman, Tr. 9369). DDR2 SDRAs continue to have three bits in the mode register reserved for burst length, allowing for up to eight different burst length values. (R 2099- 14 at 21; Soderman, Tr. 9370). DDR2 SDRAs currently require burst lengths of four and eight. (RX 2099- 14 at 21; Soderman, Tr. 9369). This may change in the future; thus the flexibility provided by the mode register is very important. (Soderman, Tr. 9370). 1225. There would have been an increase in design, photo tooling, and qualification costs because multiple products would have had to be designed and manufactured rather than just one product. (Geilhufe, Tr. 9679, 9682- , 9690). 1226. There would have been a decrease in testing costs due to the fact that each part would have had to be tested for a single burst length rather than multiple burst lengths. (Geilhufe Tr. 9594). 1227. There would have been additional inventory cost due to four different burst lengths parts being manufactured, one less than the number of required and optional burst lengths in the original SDRA standard, instead of a single programmable burst length part. (Geilhufe Tr. 9595; JX 56 at 114). There would be an "economic disadvantage" tfom having multiple part numbers corresponding to different burst lengths. (Kellogg, Tr. 5119). 1228. The fixed burst length alternative would have resulted in the following approximate net costs compared to SDRA in the mid- 1990' , assuming a first-tier DRA manufacturer and a product that is already well down the learnng curve with a volume of twenty millon unit volume, that is, a product that has already realized its cost improvement: $100 000 increase in product design costs per latency; $50 000 increase in photo tooling costs per latency; one cent decrease per unit in testing costs at wafer sort; three cents per unit increase in inventory costs; and $250 000 increase in qualification costs per latency. (Geilhufe, Tr. 9562- , 9594-95). 1229. The net increase in variable costs for the fixed burst length alternative is, therefore approximately two cents per unit. The total cost increase is approximately four cents per unit 180 calculated by converting the fixed costs to per unit costs through division by twenty millon (the unit production run) and adding the resulting per unit fixed costs to the per unit variable costs. (Geilhufe, Tr. 9595-96). 1230. Ifboth CAS latency and burst length were fixed, one would need to multiply the number of latencies by the number of burst lengths to calculate the total number of parts required. For example, if there were three latencies and four burst lengths, twelve parts would be required. (Geilhufe, Tr. 9601). Fixing both CAS latency and burst length would thus increase inventory costs by far more than the increase that would result tfom fixing CAS latency or burst length, but not both. (Geilhufe, Tr. 9601). Complaint Counsel Did Not Prove That Programming Burst Length With Fuses Was a Viable Alternative 1231. Professor Jacob' s proposed alternative of setting burst length with fuses is similar to his corresponding proposed alternative for programmng CAS latency with fuses. (Jacob Tr. 5403). 1232. Professor McMee did not testify that this alternative was commercially viable. (McMee, Tr. 7372). 1233. Once the fuse is blown, the DRA becomes a fixed burst length part under this alternative. (Jacob, Tr. 5404; Soderman, Tr. 9370). As with fixing the CAS latency, having multiple fixed burst length parts would lead to logistical diffculties exacerbated by the fact that the fuse could not be blown by OEMs. (Soderman, Tr. 9370-71; Kellogg, Tr. 5142). 1234. There would have been an increase in design costs due to the design effort to provide the fuses required. (Geilhufe, Tr. 9575, 9584-85). 1235. There would. have been increased inventory and qualification costs of the same magnitude as the corresponding costs for the fixed burst length alternative because, once the fuse is blown, the part would be a fixed burst length part. (Geilhufe, Tr. 9585-89). 1236. Setting burst length by blowing fuses would have resulted in the following approximate net costs compared to SDRA in the mid- 1990' , assuming a first-tier DRA manufacturer using existing laser fuse technology and a product that is already well down the learnng curve with a volume of twenty millon unit volume, that is, a product that has already realized its cost improvement: $100 000 increase in product design costs per latency; three cents per unit increase in inventory costs; and $250 000 increase in qualification costs per latency. (Geilhufe, Tr. 9562- , 9596-98). 1237. The net increase in variable costs for the alternative of setting burst length by blowing fuses is, therefore, approximately three cents per unit. The total cost increase is 181 approximately five cents per unit calculated by converting the fixed costs to per unit costs through division by twenty millon (the unit production run) and adding the resulting per unit fixed costs to the per unit variable costs. (Geilhufe, Tr. 9598). 1238. If the DRA manufacturer did not have antifuse or electrically blown fuse technology available and wished to use that technology, adding it to the manufacturing process would entail several millon dollars in development costs in addition to the costs above. (Geilhufe, Tr. 9583-84). Complaint Counsel Did Not Prove That Using Dedicated Pins To Identify Burst Length Was a Viable Alternative 1239. Professor Jacob' s proposed alternative of using an existing or a new dedicated pin to identify burst length is similar to his corresponding proposed alternative for using pins to identify CAS latency. (Jacob, Tr. 5405). 1240. As with the use of pins to set CAS latency, this alternative would lead to additional costs associated with adding pins to the DRA, wiring to the module and the motherboard, and adding pins to the controller. (Soderman, Tr. 9371). 1241. When asked about the advantages of using pins to set burst length, Gordon Kelley of IBM responded: I can t think of a lot of advantages compared to the programmable feature, which did not require a pin. I can think of the disadvantage that having a pin or using up a pin to do burst length selection was not a thing that we did easily, because once you use that pin up for a function, you don t have it available to you in the future for generation advance. As the memory densities increase, we need pins for more addressing of more address locations and those pins are very valuable for that feature, so this would have limited the number of generations of DRA design that we could have used if we were to use up this pin. (G. Kelley, Tr. 2552-53). 1242. Moreover, this alternative, upon a formal iningement analysis, might be determned to be covered by claim 1 of US. Patent No. 6 324 120, assigned to Rabus. (RX 2099-52 at 31-32; Soderman, Tr. 9371-72). 1243. Programmng burst length by using dedicated pins would have resulted in the following approximate net costs compared to SDRA in the mid- 1990s, assuming a first-tier DRA manufacturer and a product that is already well down the learnng curve with a volume of 182 twenty millon unit volume, that is, a product that has already realized its cost improvement: 2 cents in increased packaging costs per unit due to an additional two pins. (Geilhufe, Tr. 9562- 9599). 1244. Although SDRAs use three bits to program burst length, the cost calculation above involves the addition of only two pins based on the assumption that if pins were being used to set burst length, they would also be used to set CAS latency. (Geilhufe, Tr. 9599). Because pins have to be added in even increments, four pins were added to program CAS latency although only three were required. That extra pin, plus two additional pins, are suffcient to set burst length. (Geilhufe, Tr. 9599). Ifburst length were being set using pins, but not CAS latency, then an additional four pins would be required to achieve the same degree of flexibility as provided in the SDRA standard. (Geilhufe, Tr. 9599-9600). 1245. As in the case of using dedicated pins for CAS latency, the estimated two cent increase cost for this alternative is very conservative. (Geilhufe, Tr. 9599). Complaint Counsel Did Not Prove That Explicitly Identifying Burst Length in the Read Command Was a Viable Alternative 1246. Professor Jacob' s proposed alternative of identifying burst length in the read command is similar to his corresponding proposed alternative for identify CAS latency in the read command. (Jacob, Tr. 5407). 1247. However, claim 1 of the ' 120 patent, reproduced above, upon a formal intingement analysis, might be determned to cover "receiving block size information" including when the block size (equivalently, burst length) information is embedded in a read command. (R 2099-52 at 31-32; Soderman, Tr. 9373-74). Complaint Counsel Did Not Prove That Using a Burst Terminate Command Was a Viable Alternative 1248. Professor Jacob' s proposed alternative of using a burst terminate command rather than programmng burst length through the mode register would involve defining all parts to have a fixed, long burst length and then sending a command to terminate the burst if a shorter burst length were desired. (Jacob, Tr. 5409). 1249. A burst terminate command is an optional feature in SDRAs. (CX 234 at 161). The burst terminate command is required in DDR SDRAs, but can be used only to terminate read" bursts, not "write" bursts. (CX 234 at 174). Although DDR SDRAs have this burst terminate command available, DDR SDRAs program burst length in the mode register. (CX 234 at 150). 183 1250. A burst length of one would not have been possible with a burst termnate command because when a read command is issued it takes one cycle to execute before a burst terminate command could be encountered and, at that point, there are already two bits of data coming out. (Geilhufe, Tr. 9598-99). 1251. Professor Jacob' s proposed alternative of using a burst termnate command would lead to ineffciencies on the bus. (Jacob, Tr. 5411). For example, termnating a read burst when the next command is a write leads to ineffcient bus utilization because data already in the pipeline to be read out must be cleared before data can be written to the DRA. (Soderman, Tr. 9374- 76). Moreover, when the burst termnate command was on the bus, the controller would not be able to send a command to another bank. (Jacob, Tr. 11126). 1252. In fact, according to a study performed by Professor Jacob and a graduate student this alternative could lead to a ten to fifteen percent decrease in the effciency of the system. (Jacob, Tr. 5604-06). 1253. JEDEC participants considered burst termnate an "internal device timing nightmare." (CX 415 at 10). 1254. Steve Polzin of AM testified that use of a burst terminate command would interfere with pipelining and make the system less effcient overall. (polzin, Tr. 4038-40). 1255. The JEDEC Future DRA Task Group considered eliminating the burst termnate command, also known as burst interrupt, tfom DDR2 because at "high data rates burst interrupt commands are ofless value, and are more diffcult to engineer. " (CX 392 at 5). The Task Group also noted that elimination of burst termnate would reduce test costs and increase yield due to elimination of speed critical path. (RX 2234 at 10). 1256. Although JEDEC retained some form of burst terminate in DDR2 SDRA, the timing diffculties led JEDEC to limit its use. (Soderman, Tr. 9376-77). As Joe Macri, chairman of the JEDEC Future DRA Task Group focusing on DDR2, testified: Well, SDRA and DDR had a very general purpose interrupt. Essentially you could interrupt the DRA anywhere. And that' diffcult, you know, it' s like in the middle of a sentence, getting interrupted, and it' s just diffcult to figure out where to stop. If you can only be interrupted at a particular place, in a very precise place and under precise conditions, then it makes it much easier to do the - the burst interrpt. (Macri, Tr. at 4774 (in camera)). Thus, in the DDR2 standard, burst termnate can be used only to truncate a burst of eight to four, and it can be used only when reads are followed by reads or writes are followed by writes, not when a read is followed by a wrte or a write is followed by a 184 read. (RX 2099-39 at 63; Soderman, Tr. 9376-77). Despite including this limited form of a burst termnate command in the DDR2 standard, JEDEC also included the programmable burst length feature. (RX 2099-39 at 20). Complaint Counsel Did Not Prove That Using CAS Pulse To Control Data Output Was a Viable Alternative 1257. Professor Jacob' s proposed alternative of using a CAS pulse to control data output involves toggling the CAS line to the DRA once for each bit of data desired - thus, if a burst of four were required, the CAS line would be toggled four times. (Jacob, Tr. 5411- 12). 1258. This alternative would not work as Professor Jacob described it because it is not clear how the DRA would be able to determine whether a signal on the CAS line were intended to be a "toggle" that was part of a burst of data or a new command. (Soderman, Tr. 9378-79). Sophisticated additional circuitry would have to be added to allow the DRA to recognize the toggling of the CAS line, and that would add cost and create testing problems. (Soderman Tr. 9379). 1259. In addition, this alternative would not allow effcient interleaving between banks without adding more CAS lines. (Soderman, Tr. 9379-80). Currently, while one bank of an SDRA is reading out data, the CAS line can be used to send a command to a second bank, a process known as interleaving. Under the proposed CAS pulse alternative, the CAS line would be toggling in connection with the burst and additional CAS lines would have to be added to the other banks to enable this sort of operation. (Soderman, Tr. 9379-80). Because there are four banks on each DRA, three CAS lines would have to be added requiring additional pins on the DRA and the controller, as well as additional circuitry on the DIMs and the motherboard. (Soderman, Tr. 9380). Given the Cost-Performance Differences, an Economically Rational DRAM Manufacturer Would Have Adopted and Licensed the Rambus Technologies Incorporated In SDRAM If It Had Known Of Rambus s Royalty Rates In Advance 1260. JEDEC-compliant SDRA parts use two of the four Rambus technologies at issue: programmable CAS latency and programable burst length. In order to determine whether the use of alternatives to the Rambus technologies used in SDRA is more costly than paying the Rambus royalties, one can determne the additional variable costs associated with the alternatives and compare them to the Rambus royalties that would be paid under a license tfom Rambus. (Rapp, Tr. 9830-33). Costs for alternatives to different features are additive; that is, to calculate the costs associated with implementing alternatives to more than one feature simultaneously, one would simply add the costs associated with the individual alternatives. (Geilhufe, Tr. 9614). 185 1261. To make this comparison, the total additional cost of each alternative is divided by the weighted average of the sellng price ("ASP") of SDRA for the period 1996 to 2006. (Rapp, Tr. 9816- , 9830-33). For SDRA, the ASP is $4. 87. (Rapp, Tr. 9816- 17). This calculation shows the additional cost of the alternative as a percentage of sellng price. 1262. The Rambus royalty rate for the use of its technologies in SDRA is 0.75%. (Rapp, Tr. 9832). 1263. The alternatives for programmable CAS latency identified as "commercially viable by Complaint Counsel' s economic expert were: fixed CAS latency, explicitly identify latency in the read command, programmng latency with fuses, and using multiple pins to set a latency value. (Rapp, Tr. 9810- 11; McMee, Tr. 7354-63). 1264. The total additional incremental costs associated with the use of the fixed latency alternative is four cents per part. (Rapp, Tr. 9814). This total consists of the following additional incremental costs per part: a one cent wafer sort cost savings, a three cent good die yield cost increase, and a two cents inventory cost increase. (Rapp, Tr. 9814). As a percentage of ASP this total additional incremental cost is 0. 82%. (Rapp, Tr. 9817). 1265. The total additional incremental costs associated with the use of the alternative of explicitly identifying latency in the read command is one cent per part, which is the additional incremental costs associated with packaging. (Rapp, Tr. 9814- 15). As a percentage of ASP, this total additional incremental cost is 0.21%. (Rapp, Tr. 9817). 1266. The total additional incremental cost associated with the use of the alternative of programng latency with fuses is six cents per part. (Rapp, Tr. 9815). This total consists of the following additional incremental costs per part: a one cent wafer sort cost increase, a three cents good die yield cost increase, and a two cents inventory cost increase. (Rapp, Tr. 9815). As a percentage of ASP, this total additional incremental cost is 1.23%. (Rapp, Tr. 9817- 18). 1267. The total additional incremental costs associated with the use of the alternative of using multiple pins to set latency is four cents per part, which is the additional incremental costs associated with packaging. (Rapp, Tr. 9815). As a percentage of ASP, this total additional incremental cost is . 82%. (Rapp, Tr. 9818). 1268. In addition to the additional incremental costs, each of the alternatives for programmable CAS latency either has performance disadvantages when compared to Rambus technology or is potentially covered by Rambus s patents. (Rapp, Tr. 9819-23). 1269. The alternatives for programmable burst length identified as "commercially viable by Complaint Counsel' s economic expert were: fixed burst length, explicitly identify burst length in the read command, using a burst termnate command, and using multiple pins to set the burst length. (Rapp, Tr. 9810- 11; McMee, Tr. 7366-72). 186 1270. The total additional incremental costs associated with the use of the fixed burst length alternative is two cents per part. (Rapp, Tr. 9824-25). This total consists of the following additional incremental costs per part: a one cent wafer sort cost savings and a three cents inventory cost increase. (Rapp, Tr. 9825). As a percentage of ASP, this total additional incremental cost is 0.41%. (Rapp, Tr. 9825). 1271. The total additional incremental costs associated with the use of the alternative of explicitly identifying burst length in the read command is one cent per part, which is the additional incremental costs associated with packaging. (Rapp, Tr. 9825-26). As a percentage of ASP, this total additional incremental cost is 0.21%. (Rapp, Tr. 9826). 1272. There is no additional incremental cost associated with the use of the alternative of using a burst terminate command to set burst length. (Rapp, Tr. 9826). As discussed above, this alternative suffers tfom performance drawbacks. 1273. The total additional incremental costs associated with the use of the alternative of using multiple pins to set latency is two cents per part, which is the additional incremental costs associated with packaging. (Rapp, Tr. 9826). As a percentage of ASP, this total additional incremental cost is .41%. (Rapp, Tr. 9826). 1274. In addition to the additional incremental costs, each of the alternatives for programmable burst length either has performance disadvantages when compared to Rambus' s technology or is potentially covered by Rambus s patents. (Rapp, Tr. 9828-30). 1275. The most costly alternatives to the two identified Rambus technologies that are used in JEDEC-compliant SDRA that are not covered by Rambus s patents are the use offuses to set latency and the use of fixed burst length. (Rapp, Tr. 9832). The total additional incremental cost of using these two alternatives is eight cents per part. (Rapp, Tr. 9832). As a percentage of ASP, this additional incremental cost is 1.64%, which exceeds the 0.75% Rambus royalty rate. (Rapp, Tr. 9832). 1276. The least costly alternatives to the two Rambus technologies that are used in JEDEC-compliant SDRA that are not covered by Rambus s patents are the use offixed CAS latency and the use of a burst termnate command to set burst length. (Rapp, Tr. 9831). The total additional cost of using these two alternatives is four cents per part. (Rapp, Tr. 9831-32). As a percentage of ASP, this additional incremental cost is 0.82%, which exceeds the 0.75% Rambus royalty rate. (Rapp, Tr. 9832). 1277. In order to determne what royalty a rational decision-maker would have expected Rambus to charge (in the absence of direct knowledge), the standard assumption and methodology in economics is to assume that the royalty rate actually charged is the best estimate of the royalty rate a decision-maker would have expected at an earlier time. (Rapp, Tr. 10207- 187 09). Similarly, the standard assumption and methodology in economics is to assume that the actual weighted average sellng price over the product life cycle is the best estimate of an ASP that a decision-maker would have predicted in advance. (Rapp, Tr. 10212- 13). Using the standard assumptions and methodology in economics, a rational DRA manufacturer or group of manufacturers would have expected the additional costs of any alternatives to outweigh the costs ofRambus s royalties. 1278. Even without any reference to performance penalties, a rational manufacturer or group of manufacturers in JEDEC would have chosen to take a license tfom Rambus at 0. 75% for SDRA rather than use any combination of the alternatives identified by Complaint Counsel's economic expert as "commercially viable" that are not covered by Rambus s patents because all of those alternatives are more costly than licensing the Rambus technologies for SDRA. (Rapp, Tr. 9833). Taking performance issues into account would have reinforced the decision to license rather than to substitute any of these alternatives because most of the alternatives have performance problems as well. (Rapp, Tr. 9833). 1279. Accordingly, a rational standard setting organization that knew that Rambus had patent interests on those two technologies but did not know precisely what Rambus s royalty rates would be to license the technologies would have selected the Rambus technologies. (Rapp, Tr. 9838-39). That is true even if the standard setting body were acting in a satisficing manner. (Rapp, Tr. 9839-40). If satisficing means that small cost differences are overlooked, then a satisficing standard setting body would be indifferent to the prospect of paying royalties; therefore, the theory of satisficing does not contribute to the analysis. (Rapp, Tr. 9839-40). Complaint Counsel Did Not Prove That There Were Viable Alternatives To the Specified Rambus Technologies Adopted In DDR SDRAM Dual-Edge Clocking 1280. Complaint Counsel, through Professor Jacob, have suggested the following possible alternatives to dual-edge clocking in DDR SDRAs: (1) Interleave on-chip banks; (2) Interleave on-module ranks; (3) Increase the number of pins on the DRA; (4) Increase the number of pins on the module; (5) Double the clock tfequency; 188 (6) Use simultaneous bidirectional input/output; (7) Use toggle mode. (Jacob, Tr. 5415-38). Complaint Counsel Did Not Prove That Interleaving On-Chip Banks Was a Viable Alternative 1281. Professor Jacob' s alternative of interleaving on-chip banks involves sending a clock signal to one bank on the DRA and a second clock signal, a delayed version of the first to another bank. (Jacob, Tr. 5419- , 5614). Data would then be output or input on only a single edge of each clock signal, alternating between the two banks. (Jacob, Tr. 5419- , 5614). 1282. Professor McMee did not testify that interleaving on-chip banks was a commercially viable alternative. (McMee, Tr. 7376-81). 1283. Effcient implementation of interleaving on-chip banks would stil require dual-edge clocking and, therefore, is not an alternative. (Soderman, Tr. 9366). That is because the successive data signals tfom each bank should be given equal amounts oftime on the bus. If one bank were given a shorter time window for detection of data signals than the other, the data given the shorter time window might not be detected accurately; if, the data could be detected accurately in such a short time window, then it would be more effcient to restrict both banks to such a time window and run the bus at a faster speed. (Soderman, Tr. 9384-85). Also, a multiplexer would be used to select which bank is outputting data onto the bus at a given time. (Soderman, Tr. 9384). But the multiplexer must have a timing reference to tell it when to switch tfom one bank to the other. If one of the two clocks required by Professor Jacob' s alternative is used for this reference, then data wil be output onto the bus on both the rising and fallng edge of this clock (since the fallng edge of one of these clocks corresponds to the rising edge of the other); if, on the other hand, a third clock (not specified by Professor Jacob) is used to time the multiplexer, data would have to be output on the rising and fallng edges of that clock. (Soderman, Tr. 9384-86). 1284. Even if interleaving on-chip banks did not require dual-edge clocking, it might stil not be an alternative to Rambus s technology, because, upon a formal iningement analysis, it might be determined to be covered by US. Patent No. 5 915 105 (the ' 105 patent), assigned to Rambus. (R 1472). 1285. Professor Jacob did not consider the ' 105 patent when he proposed interleaving on-chip bans as an alternative. (Jacob, Tr. 5615- 16). 1286. Performance disadvantages of interleaving on-chip banks include significant increased power dissipation because of the power consumed by the additional clocks and the fact 189 that two banks are being accessed alternately. Keeping both banks active doubles the number of precharge cycles, and the precharge operation may be the most power consuming part of the whole DRA operation. (Soderman, Tr. 9387). 1287. There would have had to be a significant design effort for this alternative. (Geilhufe, Tr. 9602-03). 1288. There would have been a reduction in good die yield due to additional critical die area. (Geilhufe, Tr. 9603-04). So-called "redundancy technology" can be used to replace a defective part of the memory array on a DRA, but the peripheral circuitry is "critical" in the sense that a defect in that circuitry wil cause the unit to fail. (Geilhufe, Tr. 9603). The additional peripheral circuitry that would have been required to implement this alternative - such as multiplexing circuitry and timing circuitry - is critical in nature and defects in this circuitry would have reduced the good die yield. (Geilhufe, Tr. 9603-04). 1289. This alternative would have also complicated final testing and led to a slightly higher fall-out at that stage due to the necessity to activate two banks and to test the additional clocking circuitry. (Geilhufe, Tr. 9604). 1290. The alternative of interleaving on-chip banks would have resulted in the following approximate net costs compared to DDR SDRA in the late 1990' , assuming a first-tier DRA manufacturer and a product that is already well down the learning curve with a volume of twenty million unit volume, that is, a product that has already realized its cost improvement: $250 000 increase in product design costs; three cents per unit cost increase due to reduced good die yield; two cents per unit increase in final testing and good unit yield costs. (Geilhufe, Tr. 9562- 9602-04). 1291. The net increase in variable costs for the alternative of interleaving on-chip banks , therefore, approximately five cents per unit. The total costs increase is approximately six cents per unit, calculated by converting the fixed costs to per unit costs through division by twenty millon (the unit production run) and adding the resulting per unit fixed costs to the per unit variable costs. (Geilhufe, Tr. 9604-05). Complaint Counsel Did Not Prove That Interleaving On- Module Ranks Was a Viable Alternative 1292. Professor Jacob' s proposed alternative of interleaving banks on the DIM memory module is similar to his proposed alternative of interleaving on-chip banks except that data tfom different chips in a module, rather than data tfom different banks on the same chip, would be interleaved. (Jacob, Tr. 5426). 1293. Implementing this technology would require high speed bidirectional switches or multiplexers. (Soderman, Tr. 9389). Such bidirectional switches would require sophisticated 190 engineering and would add appreciable cost. (Soderman, Tr. 9389). Moreover, additional hardware would be required to drive the switches. (Soderman, Tr. 9389). 1294. Professor Jacob testified that this alternative would have significant advantages and that the only disadvantage would be a slight complication of the memory module because of an extra clock line. (Jacob, Tr. 5427-28). Professor Jacob did not testify about any need for expensive high speed switches. (Jacob, Tr. 5427-28). 1295. Unlike most of Professor Jacob' s proposed alternatives, his opinion about this alternative can be tested because a company, Kentron Technologies, Inc. ("Kentron ), has actually tried to implement the alternative of interleaving on module ranks. (Soderman Tr. 9388). 1296. Kentron s "QBM' technology involves interleaving between chips on the module. (Goodman, Tr. 5997 6002-03). Robert Goodman, Kentron s Chief Executive Offcer, testified that the QBM technology requires the use of advanced switches. (Goodman, Tr. 6082). 1297. Each module would require eight switches at a dollar a piece in high-volume production, for a total of eight dollars per module. (Goodman, Tr. 6046- , 6083). Additional circuitry, such as a PLL on the module is also required. (Goodman, Tr. 6048). 1298. Although Kentron now uses DDR SDRA chips in its QBM technology, it initially called the technology "DBR" for "double bus rate" and used SDRA chips. (CX 409 at 2). Kentron asserted that it could achieve the "same performance as 'DDR' using standard SDRA single data rate. " (CX 409 at 2). 1299. t (R 1976 at 49 (in camera)). 1300. AM' s preliminary evaluation of the Kentron QBM technology concluded that it would have signal integrity problems. (Polzin, Tr. 4035-36). 1301. Kentron had no customers for its QBM technology. (Goodman, Tr. 6008). 191 1302. Interleaving on-module ranks suffers tfom additional disadvantages. First, it would lead to a less flexible memory increment: " (b )ecause high bandwidth is achieved by interleaving between DRAs, twice as many DRAs would be required on the DIM to achieve the same bandwidth as is available using dual-edge clocking." (Soderman, Tr. 9389-90). 1303. Moreover, this alternative would not be available in all applications since many applications do not use modules at all but, rather, have the DRA soldered directly onto the motherboard. (Soderman, Tr. 9390-91; Wagner, Tr. 3871-72). 1304. The alternative of interleaving on-module ranks would have resulted in the following approximate net costs compared to DDR SDRA in the late 1990' , assuming a firsttier DRA manufacturer and a product that is already well down the learning curve with a volume of twenty millon unit volume, that is, a product that has already realized its cost improvement: four dollars per module for multiplex and driver circuitry. (Geilhufe, Tr. 9562- 9605-06). 1305. This four dollar per module cost translates into a twenty-five cent per DRA cost for DIMs, which are memory modules containing 16 DRAs each. (Geilhufe, Tr. 9606). This twenty-five cent increase is a variable cost. Complaint Counsel Did Not Prove That Increasing the Number of Pins on the DRAM Was a Viable Alternative 1306. Professor Jacob' s proposed alternative of increasing the number of pins per DRA involves achieving high bandwidth by using only a single edge of a clock but doubling the number of data pins. (Jacob, Tr. 5429). 1307. Professor McMee did not testify that increasing the number of pins on the DRA is commercially viable. (McMee, Tr. 7376-81). 1308. In addition to doubling the number of data pins, this alternative would require increasing the number of power and ground pins in order to support the added data pins. (Jacob Tr. 5429-30). The number of pads and receivers on the DRA would also have to be increased leading to an increase in the size of the DRA die and the size ofthe package. (Jacob, Tr. 5430- 31). 1309. The additional data signals would toggle very fast and cause noise that could perturb the DRA or other circuitry on the board. (Jacob, Tr. 5430-31). 1310. Tom Landgraf of Hewlett-Packard testified that his company was in favor of including dual-edged clocking in the DDR standard because of cost concerns. (Landgraf, Tr. 1709). Landgraf explained: 192 In DDR, double data rate memory, you need -- you re essentially transitioning data twice as fast as at a single data rate, and since memory systems tend to be very cost-competitive, one of our goals was to minimize the number of new pins we had to add to the next generation of memory. So, by using the double edged clock to transfer data, we were using the package and the pins more effciently. (Landgraf, Tr. 1709- 10). 1311. The alternative of increasing the number of pins on the DRA would be very expensive because of the number of additional pins required. (Soderman, Tr. 9391-92). For example, DRAs with 16 data pins would have to have 16 additional data pins, plus additional power and ground pins. (Soderman, Tr. 9391-92). Moreover, the pins would need to be interconnected through the DIM to the motherboard, increasing the cost of the whole system. (Soderman, Tr. 9392). 1312. There would have been additional product design costs because of the significant design effort associated with adding 16 input/output drivers and related multiplexing circuitry. (Geilhufe, Tr. 9607). 1313. There would have been a reduction in good die yield because of the considerable amount of critical die area added by the additional input/output circuitry. (Geilhufe, Tr. 9607). 1314. There would have been additional packaging costs associated with a more sophisticated and packaging technology known as a "ball grid array," which would have been required by the addition of 16 input/outputs. (Geilhufe, Tr. 9607-08). 1315. The alternative of increasing the number of pins on the DRA, assuming that the data width would be doubled tfom 16 to 32, would have resulted in the following approximate net costs compared to DDR SDRA in the late 1990' , assuming a first-tier DRA manufacturer and a product that is already well down the learning curve with a volume of twenty millon unit volume, that is, a product that has already realized its cost improvement: $250 000 increase in product design costs; five cent per unit cost increase due to reduced good die yield; twenty-five cent per unit increase in packaging costs. (Geilhufe, Tr. 9562- , 9607-08). 1316. The net increase in variable costs for the alternative of increasing the number of pins on the DRA is, therefore, approximately thirty cents per unit. The total cost increase is approximately thirty-one cents per unit, calculated by converting the fixed costs to per unit costs through division by twenty millon (the unit production run) and adding the resulting per unit fixed costs to the per unit variable costs. (Geilhufe, Tr. 9579). 193 -;, ..; Complaint Counsel Did Not Prove That Increasing the Number of Pins on the Module Was a Viable Alternative 1317. Professor Jacob' s proposed alternative of increasing the number of pins per module would not change the single data rate DRA at all but would achieve the desired bandwidth by adding data pins to the module. (Jacob, Tr. 5431). 1318. Professor McMee testified that increasing the number of pins on the module is not commercially viable. (McMee, Tr. 7378). 1319. This alternative would require 128 wires on the motherboard and 128 pins on the memory controller. (Jacob, Tr. 5432-33). 1320. This alternative wou